DAC7800

DAC7801
DAC7802
SBAS005B – JANUARY 1990 – REVISED FEBRUARY 2004

Dual Monolithic CMOS 12-Bit Multiplying

DIGITAL-TO-ANALOG CONVERTERS

FEATURES APPLICATIONS
● TWO DACs IN A 0.3" WIDE PACKAGE ● PROCESS CONTROL OUTPUTS
● SINGLE +5V SUPPLY ● ATE PIN ELECTRONICS LEVEL SETTING
● HIGH-SPEED DIGITAL INTERFACE: ● PROGRAMMABLE FILTERS
Serial—DAC7800 ● PROGRAMMABLE GAIN CIRCUITS
8 + 4-Bit Parallel—DAC7801
● AUTO-CALIBRATION CIRCUITS
12-Bit Parallel—DAC7802
● MONOTONIC OVER TEMPERATURE
● LOW CROSSTALK: –94dB min
● FULLY SPECIFIED OVER –40OC TO +85OC

DESCRIPTION
The DAC7800, DAC7801 and DAC7802 are members of a wide plastic DIP. The DAC7802 has a single-buffered 12-bit
new family of monolithic dual 12-bit CMOS multiplying Digi- data word interface. Parallel data is loaded (edge triggered)
tal-to-Analog Converters (DACs). The digital interface speed into the single DAC register for each DAC. The DAC7802 is
and the AC multiplying performance are achieved by using packaged in a 24-pin 0.3" wide plastic DIP.
an advanced CMOS process optimized for data conversion
circuits. High stability on-chip resistors provide true 12-bit
integral and differential linearity over the wide industrial
DAC7802 VREF A RFB A
temperature range of –40°C to +85°C. 12
12-Bit Interface
IOUT A
The DAC7800 features a serial interface capable of clocking-
in data at a rate of at least 10MHz. Serial data is clocked 12-Bit MDAC
WR

CSA

CSB

12 AGND A
DAC A
(edge triggered) MSB first into a 24-bit shift register and then
latched into each DAC separately or simultaneously as DAC7801
VREF B RFB B
required by the application. An asynchronous CLEAR control 8 8-Bit Interface
8 Bits + 4 Bits
is provided for power-on reset or system calibration func- IOUT B
tions. It is packaged in a 16-pin 0.3" wide plastic DIP. 12-Bit MDAC
CS
CLR
WR
UPD
A0
A1

12 AGND B
DAC B
The DAC7801 has a 2-byte (8 + 4) double-buffered interface.
Data is first loaded (level transferred) into the input registers Serial DAC7800
in two steps for each DAC. Then both DACs are updated Serial Interface
simultaneously. The DAC7801 features an asynchronous
CLEAR control. The DAC7801 is packaged in a 24-pin 0.3"
CLK
UPD A
UPD B
CLR
CS

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1990-2004, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
At TA = +25°C, unless otherwise noted.

VDD to AGND ............................................................................... 0V, +7V

DISCHARGE SENSITIVITY
VDD to DGND ............................................................................... 0V, +7V This integrated circuit can be damaged by ESD. Texas Instru-
AGND to DGND ....................................................................... –0.3, VDD
Digital Input to DGND ..................................................... –0.3, VDD + 0.3
ments recommends that all integrated circuits be handled with
VREF A, VREF B to AGND .................................................................. ±16V appropriate precautions. Failure to observe proper handling
VREF A, VREF B to DGND .................................................................. ±16V and installation procedures can cause damage.
IOUT A, IOUT B to AGND ............................................................. –0.3, VDD
Storage Temperature Range ....................................... –55°C to +125°C ESD damage can range from subtle performance degradation
Operating Temperature Range ...................................... –40°C to +85°C to complete device failure. Precision integrated circuits may be
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature ................................................................... +175°C more susceptible to damage because very small parametric
changes could cause the device not to meet its published
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum specifications.
conditions for extended periods may affect device reliaiblity.

PACKAGE/ORDERING INFORMATION
SPECIFIED
RELATIVE GAIN PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT ACCURACY ERROR PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY
DAC7800KP ±1LSB ±3LSB DIP-16 N –40°C to +85°C DAC7800KP DAC7800KP Rails, 25
DAC7800LP ±1/2 LSB ±1LSB DIP-16 N DAC7800LP DAC7800LP Rails, 25
DAC7800KU — — SO-16 DW –40°C to +85°C DAC7800KU DAC7800KU/1K Tape and Reel, 1000
DAC7800LU — — SO-16 DW DAC7800LU DAC7800LU/1K Tape and Reel, 1000
DAC7801KP ±1LSB ±3LSB DIP-24 NTG –40°C to +85°C DAC7801KP DAC7801KP Rails, 15
DAC7801LP ±1/2 LSB ±1LSB DIP-24 NTG DAC7801LP DAC7801LP Rails, 15
DAC7801KU — — SO-24 DW –40°C to +85°C DAC7801KU DAC7801KU/1K Tape and Reel, 1000
DAC7801LU — — SO-24 DW DAC7801LU DAC7801LU/1K Tape and Reel, 1000
DAC7802KP ±1LSB ±3LSB DIP-24 NTG –40°C to +85°C DAC7802KP DAC7802KP Rails, 15
DAC7802LP ±1/2 LSB ±1LSB DIP-24 NTG DAC7802LP DAC7802LP Rails, 15
DAC7802KU — — SO-24 DW –40°C to +85°C DAC7802KU DAC7802KU/1K Tape and Reel, 1000
DAC7802LU — — SO-24 DW DAC7802LU DAC7802LU/1K Tape and Reel, 1000

NOTE: (1 ) For the most current specifications and package information, see the package option addendum located at the end of this data sheet.

ELECTRICAL CHARACTERISTICS
At VDD = +5VDC, VREF A = VREF B = +10V, TA = –40°C to +85°C, unless otherwise noted.

DAC7800, 7801, 7802K DAC7800, 7801, 7802L

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

ACCURACY
Resolution 12 ✻ Bits
Relative Accuracy ±1 ±1/2 LSB
Differential Nonlinearity ±1 ✻ LSB
Gain Error Measured Using RFB A and RFB B. ±3 ±1 LSB
All Registers Loaded with All 1s.
Gain Temperature Coefficient(1) 2 5 ✻ ✻ ppm/°C
Output Leakage Current TA = +25°C 0.005 10 ✻ ✻ nA
TA = –40°C to +85°C 3 150 ✻ ✻ nA

REFERENCE INPUT
Input Resistance 6 10 14 ✻ ✻ ✻ kΩ
Input Resistance Match 0.5 3 ✻ 2 %

DIGITAL INPUTS
VIH (Input HIGH Voltage) 2 ✻ V
VIL (Input LOW Voltage) 0.8 ✻ V
IIN (Input Current) TA = +25°C ±1 ✻ µA
TA = –40°C to +85°C ±10 ✻ µA
CIN (Input Capacitance) 0.8 10 ✻ ✻ pF
POWER SUPPLY
VDD 4.5 5.5 ✻ ✻ V
IDD 0.2 2 ✻ ✻ mA
Power-Supply Rejection VDD from 4.5V to 5.5V 0.002 ✻ %/%

✻ Same specification as for DAC7800, 7801, 7802K.

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DAC7800, 7801, 7802
www.ti.com SBAS005A
AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At VDD = +5VDC, VREF A = VREF B = +10V, TA = +25°C, unless otherwise noted. These specifications are fully characterized but not subject to test.

DAC7800, 7801, 7802K DAC7800, 7801, 7802L

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

OUTPUT CURRENT SETTLING TIME To 0.01% of Full-Scale 0.4 0.8 ✻ ✻ µs

RL = 100Ω, CL = 13pF

DIGITAL-TO-ANALOG GLITCH IMPULSE VREF A = VREF B = 0V 0.9 ✻ nV-s

RL = 100Ω, CL = 13pF
AC FEEDTHROUGH fVREF = 10kHz –75 –72 ✻ ✻ dB

OUTPUT CAPACITANCE DAC Loaded with All 0s 30 50 ✻ ✻ pF

DAC Loaded with All 1s 70 100 ✻ ✻ pF

CHANNEL-TO-CHANNEL ISOLATION
VREF A to IOUT B fVREF A = 10kHz –90 –94 ✻ ✻ dB
VREF B = 0V,
Both DACs Loaded with 1s
VREF B to IOUT A fVREF B = 10kHz –90 –101 ✻ ✻ dB
VREF A = 0V,
Both DACs Loaded with 1s
DIGITAL CROSSTALK Full-Scale Transition 0.9 ✻ nV-s
RL = 100Ω, CL = 13pF

✻ Same specification as for DAC7800, 7801, and 7802K.

NOTE: (1) Ensured but not tested.

DAC7800
BLOCK DIAGRAM PIN CONFIGURATION

VDD Top View DIP

12

10 UPD B
DAC7800 12
DAC B Register 15 I OUT B
Control Logic and Shift Register

12 AGND A 1 16 AGND B
16 AGND B
DAC B I OUT A 2 15 IOUT B
14 RFB B
Bit 0
R FB A 3 14 R FB B
Bit 11 13 V REF B
VREF A 4 13 VREF B
Bit 12 4 VREF A DAC7800
Bit 23 CLK 5 12 VDD
3 R FB A
DAC A
UPD A 6 11 CLR
2 I OUT A
12
Data In 7 10 UPD B
DAC A Register 1 AGND A
12 CS 8 9 DGND
6 UPD A

5 8 7 11 9

CLK CS Data CLR DGND

In

LOGIC TRUTH TABLE

CLK UPD A UPD B CS CLR FUNCTION

X X X X 0 All register contents set to 0’s (asynchronous).

X X X 1 X No data transfer.
X X 0 1 Input data is clocked into input register (location Bit 23) and previous data shifts.
X 0 1 0 1 Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.
X 1 0 0 1 Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.
X 0 0 0 1 Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)
are loaded into DAC B.
X = Don’t care. means falling edge triggered.

DAC7800, 7801, 7802 3

SBAS005A www.ti.com
DAC7800 (Cont.)
DATA INPUT FORMAT

DAC7800 Digital Interface Block Diagram

UPD B

UPD A
DAC A Register DAC B Register
LSB MSB LSB MSB

CLK
Bit Bit 24-Bit Bit Bit
Data In 23 12 Shift Register 11 0

DAC7800 Data Input Sequence

CLK

Data In
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23
MSB LSB MSB LSB
DAC B DAC B DAC A DAC A

TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.

t5

CLK 0V
PARAMETER MINIMUM
t1
t1 — Data Setup Time 15ns 5V
t2 — Data Hold Time 15ns DATA 0V
t3 — Chip Select to CLK, 15ns t3 t2
Update, Data Setup Time 5V
t4 — Chip Select to CLK, 40ns CS
Update, Data Hold Time t8 t7 t4
t5 — CLK Pulse Width 40ns UPD A 5V
t6 — Clear Pulse Width 40ns UPD B t6
t7 — Update Pulse Width 40ns 5V
CLR
t8 — CLK Edge to UPD A 15ns
or UPD B NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t R = t F = 5ns.
(2) Timing measurement reference level is VIH + V IL .
2

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DAC7800, 7801, 7802
www.ti.com SBAS005A
DAC7801
BLOCK DIAGRAM PIN CONFIGURATION
VDD Top View DIP

20

DAC7801 DAC A DAC A

MS LS
Input Input AGND A 1 24 AGND B
Reg Reg
IOUT A 2 23 I OUT B
4 8
DAC A Register 2 I OUT A RFB A 3 22 RFB B
12
UPD 1 AGND A VREF A 4 21 V REF B
19 DAC A
A1 3 R FB A CS 5 20 V DD
16
Control Logic

A0 4 V REF A DB0 6 19 UPD

15
DAC7801
CS 21 V REF B DB1 7 18 WR
5

WR 22 R FB B DB2 8 17 CLR
18

CLR DAC B 23 I OUT B DB3 9 16 A1

17
12
24 AGND B DB4 10 15 A0
DAC B Register
4 8 DB5 11 14 DB7
DAC B DAC B DGND 12 13 DB6
MS LS
Input Input
Reg Reg

14 6 12

DB7–DB0 DGND

LOGIC TRUTH TABLE

CLR UPD CS WR A1 A0 FUNCTION

1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register Loaded with DB3 (MSB) - DB0
1 1 0 0 1 0 DAC B LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register Loaded with DB3 (MSB) - DB0
1 0 1 0 X X DAC A, DAC B Registers Updated Simultaneously from Input Registers
1 0 0 0 X X DAC A, DAC B Registers are Transparent
X = Don’t care.

TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.

t1 t2
5V
A0–A1
0V
t3 t4
PARAMETER MINIMUM 5V
DATA
0V
t1 — Address Valid to Write Setup Time 10ns t5 t6
5V
t2 — Address Valid to Write Hold Time 10ns CS, UPD 0V
t3 — Data Setup Time 30ns t7
t4 — Data Hold Time 10ns 5V
WR 0V
t5 — Chip Select or Update to Write Setup Time 0ns t8
t6 — Chip Select or Update to Write Hold Time 0ns 5V
CLR 0V
t7 — Write Pulse Width 40ns
t8 — Clear Pulse Width 40ns
NOTES: (1) All input signal rise and fall times are measured from 10% to 90%
of +5V. t = t = 5ns. (2) Timing measurement reference level is VIH + VIL .
R F
2

DAC7800, 7801, 7802 5

SBAS005A www.ti.com
DAC7802
BLOCK DIAGRAM PIN CONFIGURATION
Top View DIP
VDD

21

AGND 1 24 I OUT B
12
DAC7802 IOUT A 2 23 R FB B
CK DAC A Register
12 R FB A 3 22 V REF B
2 IOUT A
DAC A V REF A 4 21 V DD
CS A 5
3 R FB A
CS A 5 20 CS B
4 V REF A
(LSB) DB0 6 19 WR
DAC7802
22 V REF B
DB1 7 18 DB11 (MSB)
23 R FB B
DB2 8 17 DB10
DAC B 24 I OUT B
CS B 20 DB3 9 16 DB9
12 1 AGND
DB4 10 15 DB8
WR 19 CK DAC B Register
DB5 11 14 DB7
12
DGND 12 13 DB6
12 18 6

DGND DB11–DB0

TIMING CHARACTERISTICS
At VDD = +5V, and TA = –40oC to +85oC.

t1 t2
5V
DATA
0V
PARAMETER MINIMUM t3 t4
5V
t1 - Data Setup Time 20ns CSA, CSB
t2 - Data Hold Time 15ns t5
5V
t3 - Chip Select to Write Setup Time 30ns WR
t4 - Chip Select to Write Hold Time 0ns
t5 - Write Pulse Width 30ns NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. tR = tR = 5ns. (2) Timing measurement reference level
VIH + VIL
is .
2

LOGIC TRUTH TABLE

CSA CSB WR FUNCTION
X X 1 No Data Transfer
1 1 X No Data Transfer
0 A Rising Edge on CSA or CSB Loads
Data to the Respective DAC
0 1 DAC A Register Loaded from Data Bus
1 0 DAC B Register Loaded from Data Bus
0 0 DAC A and DAC B Registers Loaded
from Data Bus

X = Don’t care. means rising edge triggered.

6
DAC7800, 7801, 7802
www.ti.com SBAS005A
TYPICAL CHARACTERISTICS
OUTPUT OP AMP IS OPA602.
TA = +25°C, VDD = +5V.

OUTPUT LEAKAGE CURRENT

vs TEMPERATURE THD + NOISE vs FREQUENCY
1µ –60

–65
100n
Output Leakage Current (A)

–70

THD + Noise (dB)

10n
–75

1n 1Vrms
–80
3Vrms
100p –85
6Vrms
–90
10p
–95
1p –100
–75 –50 –25 0 +25 +50 +75 +100 +125 10 100 1k 10k 100k
Temperature (°C) Frequency (Hz)

CHANNEL-TO-CHANNEL ISOLATION
vs FREQUENCY FEEDTHROUGH vs FREQUENCY
–20 0
–30 –10
–40 –20
–30
Feedthrough (dB)
–50
Crosstalk (dB)

–60 –40
–70 –50
–80 –60

–90 –70

–100 –80

–110 –90

–120 –100
1k 10k 100k 1M 10M 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

FREQUENCY RESPONSE PSRR vs FREQUENCY

+30 70

+20 CF = 0pF CF = 5pF 60

+10 50
DAC Loaded w/0s
0 40
PSRR (dB)
Gain (dB)

–10 30
CF = 10pF
–20 20

–30 10
DAC Loaded w/1s
–40 0

–50 –10
1k 10k 100k 1M 10M 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

DAC7800, 7801, 7802 7

SBAS005A www.ti.com
DISCUSSION OF constant and can be driven by either a voltage or current, AC
or DC, positive or negative polarity, and have a voltage range
SPECIFICATIONS up to ±20V.
RELATIVE ACCURACY
This term, also known as end point linearity or integral VREF A R R R
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation R RFB A
2R 2R 2R 2R 2R
from a straight line, after zero and full-scale errors have been
adjusted to zero.
IOUT A
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB. AGND
DB11 DB10 DB9 DB0
A differential nonlinearity specification of 1LSB maximum (MSB) (LSB)
ensures monotonicity.

GAIN ERROR FIGURE 1. Simplified Circuit Diagram for DAC A.

Gain error is the difference between the full-scale DAC output
and the ideal value. The ideal full scale output value for the A CMOS switch transistor, included in series with the ladder
DAC780x is –(4095/4096)VREF . Gain error may be adjusted terminating resistor and in series with the feedback resistor,
to zero using external trims, see Figures 5 and 7. RFB A, compensates for the temperature drift of the ON resis-
tance of the ladder switches.
OUTPUT LEAKAGE CURRENT
Figure 2 shows an equivalent circuit for DAC A. COUT is the
The current which appears at IOUT A and IOUT B with the DAC
output capacitance due to the N-channel switches and varies
loaded with all zeros.
from about 30pF to 70pF with digital input code. The current
OUTPUT CAPACITANCE source ILKG is the combination of surface and junction leak-
The parasitic capacitance measured from IOUT A or IOUT B to ages to the substrate. ILKG approximately doubles every 10°C.
AGND. RO is the equivalent output resistance of the DAC and it varies
with input code.
CHANNEL-TO-CHANNEL ISOLATION
The AC output error due to capacitive coupling from DAC A
to DAC B or DAC B to DAC A. R
VREF A RFB A
MULTIPLYING FEEDTHROUGH ERROR IOUT A
DIN VREF ILKG
The AC output error due to capacitive coupling from VREF to R x RO COUT
4096 R
IOUT with the DAC loaded with all zeros. AGND A

OUTPUT CURRENT SETTLING TIME

The time required for the output current to settle to within FIGURE 2. Equivalent Circuit for DAC A.
+0.01% of final value for a full-scale step.

DIGITAL-TO-ANALOG GLITCH ENERGY INSTALLATION

The integrated area of the glitch pulse measured in nanovolt-
ESD PROTECTION
seconds. The key contributor to DAC glitch is charge injected
by digital logic switching transients. All digital inputs of the DAC780x incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
DIGITAL CROSSTALK 2.5kV (using the Human Body Model, 100pF and 1500Ω).
Glitch impulse measured at the output of one DAC but caused However, industry standard ESD protection methods should
by a full-scale transition on the other DAC. The integrated be used when handling or storing these components. When
area of the glitch pulse is measured in nanovolt-seconds. not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.
CIRCUIT DESCRIPTION
POWER-SUPPLY CONNECTIONS
Figure 1 shows a simplified schematic of one half of a DAC780x.
The current from the VREF A pin is switched between IOUT A and The DAC780x are designed to operate on VDD = +5V +10%.
AGND by 12 single-pole double-throw CMOS switches. This For optimum performance and noise rejection, power-supply
maintains a constant current in each leg of the ladder regard- decoupling capacitors CD should be added as shown in the
less of the input code. The input resistance at VREF is therefore application circuits. These capacitors (1µF tantalum recom-
mended) should be located close to the DAC. AGND and

8
DAC7800, 7801, 7802
www.ti.com SBAS005A
DGND should be connected together at one point only, DATA INPUT ANALOG OUTPUT
preferably at the power-supply ground point. Separate re- MSB ↓ ↓ LSB
turns minimize current flow in low-level signal paths if properly 1111 1111 1111 –VREF (4095/4096)
connected. Output op amp analog common (+ input) should 1000 0000 0000 –VREF (2048/4096) = –1/2VREF
0000 0000 0001 –VREF (1/4096)
be connected as near to the AGND pins of the DAC780x as 0000 0000 0000 0 Volts
possible.
TABLE II. Unipolar Output Code.
WIRING PRECAUTIONS
To minimize AC feedthrough when designing a PC board, VDD VREF A
care should be taken to minimize capacitive coupling be- +5V
tween the VREF lines and the IOUT lines. Similarly, capacitive CD +
coupling between DACs may compromise the channel-to- 1µF RFB A
channel isolation. Coupling from any of the digital control or C1
data lines might degrade the glitch and digital crosstalk IOUT A 10pF
–
performance. Solder the DAC780x directly into the PC board DAC A A1
AGND A
without a socket. Sockets add parasitic capacitance (which + VOUT A
can degrade AC performance).
DAC780X RFB B

AMPLIFIER OFFSET VOLTAGE C2

IOUT B 10pF
The output amplifier used with the DAC780x should have low –
DAC B AGND B A2
input offset voltage to preserve the transfer function linearity. + VOUT B
The voltage output of the amplifier has an error component
which is the offset voltage of the op amp multiplied by
the “noise gain” of the circuit. This “noise gain” is equal to A1, A2 OPA602 or 1/2 OPA2107.
DGND VREF B DAC7802 has a single analog
(RF /RO + 1) where RO is the output impedance of the DAC common, AGND.
IOUT terminal and RF is the feedback network impedance. The
nonlinearity occurs due to the output impedance varying with FIGURE 3. Unipolar Configuration.
code. If the 0 code case is excluded (where RO = infinity), the
RO will vary from R-3R providing a “noise gain” variation VDD VIN A
between 4/3 and 2. In addition, the variation of RO is nonlinear +5V
R1
with code, and the largest steps in RO occur at major code 100Ω
CD +
transitions where the worst differential nonlinearity is also 1µF
V REF A
likely to be experienced. The nonlinearity seen at the amplifier RFB A R2
output is 2VOS – 4VOS /3 = 2VOS /3. Thus, to maintain good C1 10pF
47Ω
nonlinearity the op amp offset should be much less than IOUT A
–
1/2 LSB. DAC A A1
AGND A
+ VOUT A
UNIPOLAR CONFIGURATION DAC780X RFB B R4
Figure 3 shows DAC780x in a typical unipolar (two-quadrant)
47Ω C2 10pF
multiplying configuration. The analog output values versus IOUT B
digital input code are listed in Table II. The operational –
DAC B A2
amplifiers used in this circuit can be single amplifiers such as AGND B
+ VOUT B
the OPA602, or a dual amplifier such as the OPA2107. C1
and C2 provide phase compensation to minimize settling time V REF B
and overshoot when using a high speed operational amplifier. A1, A2 OPA602 or 1/2 OPA2107.
R3 DAC7802 has a single analog
If an application requires the DAC to have zero gain error, the 100Ω common, AGND.
DGND
circuit shown in Figure 4 may be used. Resistors R2 and R4 V IN B
induce a positive gain error greater than worst-case initial
negative gain error. Trim resistors R1 and R3 provide a FIGURE 4. Unipolar Configuration with Gain Trim.
variable negative gain error and have sufficient trim range to
correct for the worst-case initial positive gain error plus the The operational amplifiers used in this circuit can be single
error produced by R2 and R4. amplifiers such as the OPA602, a dual amplifier such as the
OPA2107, or a quad amplifier like the OPA404. C1 and C2
BIPOLAR CONFIGURATION provide phase compensation to minimize settling time and
See Figure 5 for the DAC780x in a typical bipolar (four- overshoot when using a high speed operational amplifier. The
quadrant) multiplying configuration. See Table III for the bipolar offset resistors R5–R7 and R8–R10 should be ratio-
listing of the analog output values versus digital input code. matched to 0.01% to ensure the specified gain error perfor-
mance.

DAC7800, 7801, 7802 9

SBAS005A www.ti.com
If an application requires the DAC to have zero gain error, the DATA INPUT ANALOG OUTPUT
circuit may be used, see Figure 6. Resistors R2 and R4 induce MSB ↓ ↓ LSB
a positive gain error greater than worst-case initial negative 1111 1111 1111 +VREF (2047/2048)
gain error. Trim resistors R1 and R3 provide a variable 1000 0000 0001 +VREF (1/2048)
1000 0000 0000 0 Volts
negative gain error and have sufficient trim range to correct 0111 1111 1111 –VREF (1/2048)
for the worst-case initial positive gain error plus the error 0000 0000 0000 –VREF (2048/2048)
produced by R2 and R4.
TABLE III. Bipolar Output Code.

+5V R1
VDD VREF A 20k Ω
R2
20k Ω
–
CD + A2 VOUT A
1µF R3 +
10k Ω
RFB A
C1
IOUT A 10pF
–
DAC A A1
AGND A +
DAC7802 has a single analog common, AGND.
DAC780X A1–A4, OPA602 or 1/2 OPA2107.
RFB B
C2
IOUT B 10pF
–
DAC B A3
AGND B + R4
R5 20k Ω
R6 10k Ω
20k Ω
DGND –
A4 VOUT B
VREF B +

FIGURE 5. Bipolar Configuration.

APPLICATIONS DAC1 and DAC2 can be updated in parallel with a single word
to set the center frequency of the filter. DAC 4, which makes
12-BIT PLUS SIGN DACS use of the uncommitted op amp in UAF42, sets the Q of the
filter. DAC3 sets the gain of the filter transfer function without
For a bipolar DAC with 13 bits of resolution, two solutions are
changing the Q of the filter. The reverse is also true.
possible. The addition of a precision difference amplifier and
a high speed JFET switch provides a 12-bit plus sign voltage- The center frequency is determined by fC = 1/2πRC where R is
output DAC, see Figure 7. When the switch selects the op the ladder resistance of the DAC (typical value, 10kΩ) and C
amp output, the difference amplifier serves as a noninverting the internal capacitor value (1000pF) of the UAF42. External
output buffer. If the analog ground side of the switch is capacitors can be added to lower the center frequency of the
selected, the output of the difference amplifier is inverted. filter. But the highest center frequency for this circuit will be
about 16kHz because the effective series resistance of the
Another option, see Figure 8, also produces a 12-bit plus sign
DAC cannot be less than 10kΩ.
output without the additional switch and digital control line.
Note that the ladder resistance of the DAC may vary from
DIGITALLY PROGRAMMABLE ACTIVE FILTER device to device. Thus, for best tracking, DAC2 and DAC3
See Figure 9 for the DAC780x in a digitally programmable should be in the same package. Some calibration may be
active filter application. The design is based on the state- necessary from one filter to another.
variable filter, Texas Instruments UAF42, an active filter topol-
ogy that offers stable and repeatable filter characteristics.

10
DAC7800, 7801, 7802
www.ti.com SBAS005A
 R5
+5V 20k Ω
VDD VIN A
R6
20k Ω
–
A2 VOUT A
CD + R1
+
1µF 100 Ω R7
VREF A R2 10k Ω
RFB A 47 Ω

C1
IOUT A 10pF
–
DAC A A1
AGND A +
DAC7802 has a single analog common, AGND.
DAC7802 R4 A1–A4, OPA602 or 1/2 OPA2107.
RFB B 47 Ω

C2
IOUT B 10pF
–
DAC B A3
AGND B +
R9
10kΩ
10k Ω R8
VREF B 20k Ω
DGND R3 R10
100 Ω 20k Ω
–
A4 VOUT B
VIN B +

FIGURE 6. Bipolar Configuration with Gain Trim.

+15V

2
+10V
6 REF102
+5V
4
VDD
CD VREF A
1µF
RFB A

C1
IOUT A 10pF
R
DAC A AGND A A1
R
2 ±10V
DAC780X R 6
13 Bits
3

R
Sign Control
1 INA105
DAC B DG188
AGND B

DGND VREF B DAC7802 has a single analog common, AGND.

A1 OPA602 or 1/2 OPA2107.

FIGURE 7. 12-Bit Plus Sign DAC.

DAC7800, 7801, 7802 11

SBAS005A www.ti.com
 +15V

2
+10V
6 REF102
+5V
4
VDD
CD VREF A
1µF
RFB A

C1
IOUT A 10pF
R
DAC A AGND A A1
R
2
DAC780X ±10V
RFB B R 6
13 Bits
3
C2
IOUT B 10pF R

DAC B INA105
AGND B A2
1

DGND VREF B DAC7802 has a single analog common, AGND.

A1 OPA602 or 1/2 OPA2107.

FIGURE 8. 13-Bit Bipolar DAC.

Q Adjust

VREF 2 V REF 4 R FB 4
IOUT 2 I OUT 4
DAC 2 AGND 2 DAC 4 AGND 4

f C Adjust
VREF 1 1/2 DAC780X
IOUT 1

DAC 1 AGND 1

DAC780X Low-Pass
Band-Pass
Out
High-Pass Out Out

Filter Input 13 8 7 14 1 5
R
VREF 3
I OUT 3 R C C
12
DAC 3 AGND 3

1/2 DAC780X 6
Gain Adjust 3
R R
UAF 42
2 11 4
R = 50k Ω ±0.5%
C = 1000pF ±0.5%

FIGURE 9. Digitally Programmable Universal Active Filter.

12
DAC7800, 7801, 7802
www.ti.com SBAS005A
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

DAC7800KU ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7800KU

& no Sb/Br)
DAC7800KU/1K ACTIVE SOIC DW 16 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7800KU
& no Sb/Br)
DAC7800KU/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7800KU
& no Sb/Br)
DAC7800LP NRND PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 DAC7800LP
& no Sb/Br)
DAC7800LPG4 NRND PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 DAC7800LP
& no Sb/Br)
DAC7800LU NRND SOIC DW 16 40 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7800LU
& no Sb/Br)
DAC7801KU ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7801KU
& no Sb/Br)
DAC7801KU/1K ACTIVE SOIC DW 24 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7801KU
& no Sb/Br)
DAC7801LU ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7801LU
& no Sb/Br)
DAC7802KU ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7802KU
& no Sb/Br)
DAC7802KU/1K ACTIVE SOIC DW 24 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7802KU
& no Sb/Br)
DAC7802LU ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7802LU
& no Sb/Br)
DAC7802LUG4 ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 DAC7802LU
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Feb-2020

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC7800KU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
DAC7801KU/1K SOIC DW 24 1000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
DAC7802KU/1K SOIC DW 24 1000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC7800KU/1K SOIC DW 16 1000 350.0 350.0 43.0
DAC7801KU/1K SOIC DW 24 1000 350.0 350.0 43.0
DAC7802KU/1K SOIC DW 24 1000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016A SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4220721/A 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP

(9.3)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220721/A 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP
(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220721/A 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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