DAC7714

DAC ®
771
4

Quad, Serial Input, 12-Bit, Voltage Output

DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION
● LOW POWER: 250mW (max) The DAC7714 is a quad, serial input, 12-bit, voltage
● UNIPOLAR OR BIPOLAR OPERATION output Digital-to-Analog Converter (DAC) with guar-
anteed 12-bit monotonic performance over the –40°C
● SETTLING TIME: 10µs to 0.012%
to +85°C temperature range. An asynchronous reset
● 12-BIT LINEARITY AND MONOTONICITY: clears all registers to either mid-scale (800H) or zero-
–40°C to +85°C scale (000H), selectable via the RESETSEL pin. The
● USER SELECTABLE RESET TO MID- device can be powered from a single +15V supply or
SCALE OR ZERO-SCALE from dual +15V and –15V supplies.
● SECOND-SOURCE for DAC8420 Low power and small size makes the DAC7714 ideal
for process control, data acquisition systems, and
● SMALL SO-16 PACKAGE
closed-loop servo-control. The device is available in a
SO-16 package, and is guaranteed over the –40°C to
APPLICATIONS +85°C temperature range.
● ATE PIN ELECTRONICS
● PROCESS CONTROL
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL GND VCC VREFH

● DATA ACQUISITION SYSTEMS

DAC
DAC A
Register A
VOUTA
SDI

DAC
DAC B
Register B
Serial-to- VOUTB
Parallel 12
Shift
Register

DAC
DAC C
Register C
VOUTC

CLK
CS DAC
DAC
Select DAC D
Register D
VOUTD

LOADDACS RESET RESETSEL VREFL VSS

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
http://www.burr-brown.com/ http://www.ti.com/

Copyright © 2000, Texas Instruments Incorporated PDS-1533A Printed in U.S.A. September, 2000
SBAS119
SPECIFICATIONS (Dual Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, unless otherwise noted.

DAC7714U DAC7714UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

ACCURACY
Linearity Error ±2 ±1 LSB(1)
Linearity Matching(2) ±2 ±1 LSB
Differential Linearity Error ±1 ±1 LSB
Monotonicity TMIN to TMAX 12 ✻ Bits
Zero-Scale Error Code = 000H ±2 ✻ LSB
Zero-Scale Drift 1 ✻ ppm/°C
Zero-Scale Matching(2) ±2 ±1 LSB
Full-Scale Error Code = FFFH ±2 ✻ LSB
Full-Scale Matching(2) ±2 ±1 LSB
Power Supply Sensitivity At Full Scale 10 ✻ ppm/V
ANALOG OUTPUT
Voltage Output(3) VREFL VREFH ✻ ✻ V
Output Current –5 +5 ✻ ✻ mA
Load Capacitance No Oscillation 500 ✻ pF
Short-Circuit Current ±20 ✻ mA
Short-Circuit Duration To VSS, VCC, or GND Indefinite ✻
REFERENCE INPUT
VREFH Input Range VREFL +1.25 +10 ✻ ✻ V
VREFL Input Range –10 VREFH – 1.25 ✻ ✻ V
Ref High Input Current –0.5 3.0 ✻ ✻ mA
Ref Low Input Current –3.5 0 ✻ ✻ mA
DYNAMIC PERFORMANCE
Settling Time To ±0.012%, 20V Output Step 8 10 ✻ ✻ µs
Channel-to-Channel Crosstalk Full-Scale Step 0.25 ✻ LSB
Digital Feedthrough 2 ✻ nV-s
Output Noise Voltage f = 10kHz 65 ✻ nV/√Hz
DIGITAL INPUT
Logic Levels
VIH IIH ≤ ±10µA 3.325 ✻ V
VIL IIL ≤ ±10µA 1.575 ✻ V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
VCC +14.25 +15.75 ✻ ✻ V
VSS –15.75 –14.25 ✻ ✻ V
ICC 6 8.5 ✻ ✻ mA
ISS –8 –6 ✻ ✻ mA
Power Dissipation 180 250 ✻ ✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻ ✻ °C

NOTES: (1) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within
the specified error band. (3) Ideal output voltage does not take into account zero or full-scale error.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

DAC7714 2
SPECIFICATIONS (Single Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = GND, VREFH = +10V, VREFL = 0V, unless otherwise noted.

DAC7714U DAC7714UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

ACCURACY
Linearity Error(1) ±2 ±1 LSB(2)
Linearity Matching(3) ±2 ±1 LSB
Differential Linearity Error ±1 ±1 LSB
Monotonicity TMIN to TMAX 12 ✻ Bits
Zero-Scale Error Code = 004H ±4 ✻ LSB
Zero-Scale Drift 2 ✻ ppm/°C
Zero-Scale Matching(3) ±4 ±2 LSB
Full-Scale Error Code = FFFH ±4 ✻ LSB
Full-Scale Matching(3) ±4 ±2 LSB
Power Supply Sensitivity At Full Scale 20 ✻ ppm /V
ANALOG OUTPUT
Voltage Output(4) VREFL VREFH ✻ ✻ V
Output Current –5 +5 ✻ mA
Load Capacitance No Oscillation 500 ✻ pF
Short-Circuit Current ±20 ✻ mA
Short-Circuit Duration To VCC or GND Indefinite ✻
REFERENCE INPUT
VREFH Input Range VREFL +1.25 +10 ✻ ✻ V
VREFL Input Range 0 VREFH – 1.25 ✻ ✻ V
Ref High Input Current –0.3 1.5 ✻ ✻ mA
Ref Low Input Current –2.0 0 ✻ ✻ mA
DYNAMIC PERFORMANCE
Settling Time(5) To ±0.012%, 10V Output Step 8 10 ✻ ✻ µs
Channel-to-Channel Crosstalk 0.25 ✻ LSB
Digital Feedthrough 2 ✻ nV-s
Output Noise Voltage f = 10kHz 65 ✻ nV/√Hz
DIGITAL INPUT/OUTPUT
Logic Levels
VIH IIH ≤ ±10µA 3.325 ✻ V
VIL IIL ≤ ±10µA 1.575 ✻ V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
VCC 14.25 15.75 ✻ ✻ V
ICC 3.0 ✻ ✻ mA
Power Dissipation 45 ✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻ ✻ °C

NOTES: (1) If VSS = 0V, specification applies at code 004H and above. (2) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals 0V, then one
LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error.
(5) Full-scale positive 10V step and negative step from code FFFH to 020H.

3 DAC7714
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
VCC to VSS ........................................................................... –0.3V to +32V
VCC to GND ......................................................................... –0.3V to +16V DISCHARGE SENSITIVITY
VSS to GND ......................................................................... +0.3V to –16V
VREFH to GND ....................................................................... –9V to +11V This integrated circuit can be damaged by ESD. Burr-Brown
VREFL to GND (VSS = –15V) ................................................. –11V to +9V recommends that all integrated circuits be handled with
VREFL to GND (VSS = 0V) .................................................... –0.3V to +9V
VREFH to VREFL ....................................................................... –1V to +22V
appropriate precautions. Failure to observe proper handling
Digital Input Voltage to GND .............................................. –0.3V to 5.8V and installation procedures can cause damage.
Digital Output Voltage to GND ............................................ –0.3V to 5.8V
Maximum Junction Temperature ................................................... +150°C ESD damage can range from subtle performance degradation
Operating Temperature Range ........................................ –40°C to +85°C to complete device failure. Precision integrated circuits may
Storage Temperature Range ......................................... –65°C to +150°C be more susceptible to damage because very small parametric
Lead Temperature (soldering, 10s) ............................................... +300°C
changes could cause the device not to meet its published
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” specifications.
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION
MAXIMUM MAXIMUM
LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION
ERROR LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE NUMBER RANGE NUMBER(1) MEDIA

DAC7714U ±2 ±1 SO-16 211 –40°C to +85°C DAC7714U Rails

" " " " " " DAC7714U/1K Tape and Reel
DAC7714UB ±1 ±1 SO-16 211 –40°C to +85°C DAC7714UB Rails
" " " " " " DAC7714UB/1K Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7714UB/1K” will get a single 1000-piece Tape and Reel.

ESD PROTECTION CIRCUITS

VCC
VCC

REFH
VOUT
REFL

VSS
VSS

Internal VDD

GND

Typical of Each
Logic Input Pin

DAC7714 4
PIN CONFIGURATION—U Package PIN DESCRIPTIONS—U Package

Top View SO PIN LABEL DESCRIPTION

1 VCC Positive Analog Supply Voltage, +15V nominal.

2 VOUTD DAC D Voltage Output
3 VOUTC DAC C Voltage Output
4 VREFL Reference Input Voltage Low. Sets minimum
output voltage for all DACs.
5 VREFH Reference Input Voltage High. Sets maximum
output voltage for all DACs.
VCC 1 16 RESETSEL 6 VOUTB DAC B Voltage Output

VOUTD 2 15 RESET 7 VOUTA DAC A Voltage Output

8 VSS Negative Analog Supply Voltage, 0V or –15V
VOUTC 3 14 LOADDACS
nominal.
VREFL 4 13 NIC 9 GND Ground
DAC7714U
VREFH 5 12 CS 10 SDI Serial Data Input
11 CLK Serial Data Clock
VOUTB 6 11 CLK
12 CS Chip Select Input
VOUTA 7 10 SDI
13 NIC Not Internally Connected
VSS 8 9 GND 14 LOADDACS The selected DAC register becomes transparent
when LOADDACS is LOW. It is in the latched
state when LOADDACS is HIGH.
15 RESET Asynchronous Reset Input. Sets all DAC
registers to either zero-scale (000H) or mid-
scale (800H) when LOW. RESETSEL determines
which code is active.
16 RESETSEL When LOW, a LOW on RESET will cause all
DAC registers to be set to code 000H. When
RESETSEL is HIGH, a LOW on RESET will set
the registers to code 800H.

5 DAC7714
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.

LINEARITY ERROR AND LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C Single Channel 85°C
(Typical of Each Output Channel) (Typical of Each Output Channel)
0.5 0.5
0.4 0.4
0.3 0.3
0.2
LE (LSB)

0.2

LE (LSB)
0.1 0.1
0 0
–0.1 –0.1
–0.2 –0.2
–0.3 –0.3
–0.4 –0.4
–0.5 –0.5
0.5 0.5
0.4 0.4
0.3 0.3
DLE (LSB)

DLE (LSB)
0.2 0.2
0.1 0.1
0 0
–0.1 –0.1
–0.2 –0.2
–0.3 –0.3
–0.4 –0.4
–0.5 –0.5
000H 200H 400H 600H 800H A00H C00H E00H FFFH 000H 200H 400H 600H 800H A00H C00H E00H FFFH
Digital Input Code Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C ZERO-SCALE ERROR vs TEMPERATURE
(Typical of Each Output Channel) (Code 004H)
0.5 2.0
0.4
0.3
0.2 1.5
LE (LSB)

0.1 DAC C
0
Zero-Scale Error (mV)

–0.1 1.0 DAC A

–0.2
–0.3 0.5
–0.4
–0.5
0
0.5
0.4 –0.5 DAC B
0.3
DLE (LSB)

0.2 DAC D
0.1 –1.0
0
–0.1
–0.2 –1.5
–0.3
–0.4
–0.5 –2.0
000H 200H 400H 600H 800H A00H C00H E00H FFFH –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
Digital Input Code Temperature (°C)

CURRENT vs CODE
FULL-SCALE ERROR vs TEMPERATURE All DACs Set to Indicated Code
(Code FFFH) VREFH
2.0 1.2
VREF Current (mA)

1.0
1.5 0.8
0.6
DAC C 0.4
1.0
Full-Scale Error (mV)

0.2
0
0.5 DAC B –0.2
DAC A
–0.4
0 VREFL
0
VREF Current (mA)

–0.5 –0.2
DAC D –0.4
–1.0 –0.6
–0.8
–1.0
–1.5 –1.2
–1.4
–2.0 –1.6
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 000H 200H 400H 600H 800H A00H C00H E00H FFFH
Temperature (°C) Digital Input Code

DAC7714 6
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.

POSITIVE SUPPLY CURRENT

POWER SUPPLY CURRENT vs TEMPERATURE vs DIGITAL INPUT CODE
4.5 6.00

5.00
3.5
Quiescent Current (mA)

No Load, All 4 DACs Set to Indicated Code

ICC 4.00
2.5

ICC (mA)
ICC
3.00
1.5
2.00

0.5
1.00

–0.5 0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 000H 200H 400H 600H 800H A00H C00H E00H FFFH
Temperature (°C) Digital Input Code

OUTPUT VOLTAGE vs SETTLING TIME OUTPUT VOLTAGE vs SETTLING TIME

(0V to +10V) (+10V to Code 020H)

Large Signal
Settling Time: 5V/div Large Signal
Settling Time: 5V/div
Output Voltage
Output Voltage

Small Signal Small Signal

Settling Time: 1LSB/div Settling Time: 1LSB/div

+5V +5V
LOADDACS LOADDACS
0 0
Time (2µs/div) Time (2µs/div)

OUTPUT VOLTAGE OUTPUT VOLTAGE

MID-SCALE GLITCH PERFORMANCE MID-SCALE GLITCH PERFORMANCE
Output Voltage (200mV/div)

Output Voltage (200mV/div)

7FFH to 800H 800H to 7FFH

+5V +5V
LOADDACS LOADDACS
0 0
Time (1µs/div) Time (1µs/div)

7 DAC7714
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.

OUTPUT NOISE vs FREQUENCY OUTPUT VOLTAGE vs RLOAD

1000 15

12
Code 020H
Source
Noise (nV/√Hz)

VOUT (V)
100
6

Code FFFH
3

Sink
10 0
0 0.1 1 10 100 1000 10000 0.01 0.1 1 10 100
Frequency (kHz) RLOAD (kW)

SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE POWER SUPPLY REJECTION RATIO vs FREQUENCY
20 0
Short to Ground –10
15
–20
10 –30
–40
5
PSRR (dB)
IOUT (mA)

–50 +15V
0 –60
–70
–5
–80
–10 –90
Short to VCC –100
–15
–110
–20 –120
000H 200H 400H 600H 800H A00H C00H E00H FFFH 101 102 103 104 105 106
Digital Input Code Frequency (Hz)

DAC7714 8
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.

LINEARITY ERROR AND LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C Single Channel 85°C
(Typical of Each Output Channel) (Typical of Each Output Channel)
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2

LE (LSB)
LE (LSB)

0.1 0.1
0 0
–0.1 –0.1
–0.2 –0.2
–0.3 –0.3
–0.4 –0.4
–0.5 –0.5

0.5 0.5
0.4 0.4
0.3 0.3

DLE (LSB)
DLE (LSB)

0.2 0.2
0.1 0.1
0 0
–0.1 –0.1
–0.2 –0.2
–0.3 –0.3
–0.4 –0.4
–0.5 –0.5
000H 200H 400H 600H 800H A00H C00H E00H FFFH 000H 200H 400H 600H 800H A00H C00H E00H FFFH
Digital Input Code Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE CURRENT vs CODE
Single Channel –40°C All DACs Set to Indicated Code
(Typical of Each Output Channel) VREFH
0.5 2.5
VREF Current (mA)
0.4
0.3 2.0
0.2
LE (LSB)

0.1 1.5
0 1.0
–0.1
–0.2 0.5
–0.3 0
–0.4
–0.5 –0.5
VREFL
0.5 0
VREF Current (mA)

0.4
0.3 –0.5
DLE (LSB)

0.2 –1.0
0.1
0 –1.5
–0.1
–0.2 –2.0
–0.3 –2.5
–0.4
–0.5 –3.0
000H 200H 400H 600H 800H A00H C00H E00H FFFH 000H 200H 400H 600H 800H A00H C00H E000H FFFH
Digital Input Code Digital Input Code

BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE POSITIVE FULL-SCALE ERROR vs TEMPERATURE

(Code 800H) (Code FFFH)
2.0 2.0

1.5 1.5
Bipolar Zero-Scale Error (mV)

Positive Full-Scale Error (mV)

DAC C
1.0 1.0
DAC C
0.5 0.5
DAC B
0 0

–0.5 –0.5
DAC D DAC D DAC A
–1.0 –1.0
DAC B DAC A
–1.5 –1.5

–2.0 –2.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
Temperature (°C) Temperature (°C)

9 DAC7714
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.

NEGATIVE FULL-SCALE ERROR vs TEMPERATURE

(Code 000H) POWER SUPPLY CURRENT vs TEMPERATURE
2.0 8

1.5 6
Negative Full-Scale Error (mV)

ICC

Quiescent Current (mA)

1.0 DAC C 4
DAC A
0.5 2

0 0

–0.5 –2
DAC B DAC D ISS
–1.0 –4
Data = FFFH (all DACs)
–1.5 –6
No Load
–2.0 –8
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
Temperature (°C) Temperature (°C)

OUTPUT VOLTAGE vs RLOAD SUPPLY CURRENT vs CODE

15 8
ICC
6
10
Source 4
Supply Current (mA)

No Load, All 4 DACs Set to Indicated Code

5
2
VOUT (V)

0 0

–2
–5
–4
Sink
–10 ISS
–6

–15 –8
0.01 0.1 1 10 100 000H 200H 400H 600H 800H A00H C00H E00H FFFH
RLOAD (kΩ) Digital Input Code

OUTPUT VOLTAGE vs SETTLING TIME OUTPUT VOLTAGE vs SETTLING TIME

(–10V to +10V) (+10V to –10V)

Large Signal Large Signal

Settling Time: 5V/div Settling Time: 5V/div

Small Signal
Output Voltage
Output Voltage

Settling Time: 0.5LSB/div

Small Signal
Settling Time: 0.5LSB/div

+5V +5V
LOADDACS LOADDACS
0 0
Time (2µs/div) Time (2µs/div)

DAC7714 10
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.

DUAL SUPPLY CURRENT LIMIT vs INPUT CODE

SHORT TO GROUND POWER SUPPLY REJECTION RATIO vs FREQUENCY
20 0
–10
15
–20
10 –30
–40
5

PSRR (dB)
IOUT (mA)

–50 –15V
0 –60 +15V
–70
–5
–80
–10 –90
–100
–15
–110
–20 –120
000H 200H 400H 600H 800H A00H C00H E00H FFFH 101 102 103 104 105 106
Digital Input Code Frequency (Hz)

OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE BROADBAND NOISE
Output Voltage (200mV/div)

Noise Voltage (500µV/div)

7FFH to 800H 800H to 7FFH

+5V
LOADDACS
0
Time (1µs/div) Time (1ms/div)

OUTPUT NOISE vs FREQUENCY

1000
Noise (nV/√Hz)

100

Noise at any code

10
0 0.1 1 10 100 1000 10000
Frequency (kHz)

11 DAC7714
THEORY OF OPERATION At the negative offset limit of –4LSB (–9.76mV), for the
single-supply case, the first specified output starts at code
The DAC7714 is a quad, serial input, 12-bit, voltage output 004H.
DAC. The architecture is a classic R-2R ladder configura-
tion followed by an operational amplifier that serves as a
REFERENCE INPUTS
buffer. Each DAC has its own R-2R ladder network and
output op amp, but all share the reference voltage inputs, as The reference inputs, VREFL and VREFH, can be any voltage
shown in Figure 1. The minimum voltage output (“zero- between VSS + 4V and VCC – 4V provided that VREFH is at
scale”) and maximum voltage output (“full-scale”) are set by least 1.25V greater than VREFL. The minimum output of
external voltage references (VREFL and VREFH, respectively). each D/A is equal to VREFL – 1LSB plus a small offset
The digital input is a 16-bit serial word that contains the voltage (essentially, the offset of the output op amp). The
12-bit DAC code and a 2-bit address code that selects one of maximum output is equal to VREFH plus a similar offset
the four DACs (the two remaining bits are unused). The voltage. Note that VSS (the negative power supply) must
converter can be powered from a single +15V supply or a either be connected to ground or must be in the range of
dual ±15V supply. Each device offers a reset function which –14.75V to –15.75V. The voltage on VSS sets several bias
immediately sets all DAC output voltages and internal points within the converter. If VSS is not in one of these two
registers to either zero-scale (code 000H) or mid-scale (code configurations, the bias values may be in error and proper
800H). The reset code is selected by the state of the operation of the device is not guaranteed.
RESETSEL pin (LOW = 000H, HIGH = 800H). Figures 2 The current into the reference inputs depends on the DAC
and 3 show the basic operation of the DAC7714. output voltages and can vary from a few microamps to
approximately 3mA. The reference input appears as a vary-
ANALOG OUTPUTS ing load to the reference. If the reference can sink or source
When VSS = –15V (dual supply operation), the output the required current, a reference buffer is not required. See
amplifier can swing to within 4V of the supply rails, over the “Reference Current vs Code” in the Typical Performance
–40°C to +85°C temperature range. With VSS = 0V (single- Curves.
supply operation), the output can swing to ground. Note that The analog supplies must come up before the reference
the settling time of the output op amp will be longer with power supplies, if they are separate. If the power supplies for
voltages very near ground. Care must also be taken when the references come up first, then the VCC and VSS supplies
measuring the zero-scale error when VSS = 0V. If the output will be powered from the reference via the ESD protection
amplifier has a negative offset, the output voltage may not diodes (see page 4).
change for the first few digital input codes (000H, 001H,
002H, etc.) since the output voltage cannot swing below
ground.

RF

R R R R R R R VOUT

2R 2R 2R 2R 2R 2R 2R 2R 2R

VREFH

VREFL

FIGURE 1. DAC7714 Architecture.

DAC7714 12
 +15V
DAC7714
+
1µF to 10µF 0.1µF
1 VCC RESETSEL 16

2 VOUTD RESET 15 Reset DACs(1)

0V to +10.0V
3 VOUTC LOADDACS 14 Update Selected Register
0V to +10.0V
4 VREFL NIC 13
+10.000V
0.1µF 5 VREFH CS 12 Chip Select

6 VOUTB CLK 11 Clock

0V to +10.0V
7 VOUTA SDI 10 Serial Data In
0V to +10.0V
8 VSS GND 9

NOTE: (1) As configured, RESET LOW sets all internal registers to code 000H (0V).
If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (5V).

FIGURE 2. Basic Single-Supply Operation of the DAC7714.

DAC7714
+15V
+
1µF to 10µF 0.1µF
1 VCC RESETSEL 16 +5V

–10V to +10V 2 VOUTD RESET 15 Reset DACs(1)

–10V to +10V 3 VOUTC LOADDACS 14 Update Selected Register

–10.0V 4 VREFL NIC 13

0.1µF
5 VREFH CS 12 Chip Select
+10.0V
0.1µF 6 VOUTB CLK 11 Clock

7 VOUTA SDI 10 Serial Data In

–10V to +10V
–10V to +10V 8 VSS GND 9
–15V
1µF to 10µF 0.1µF
+
NOTE: (1) As configured, RESET LOW sets all internal registers to code 800H (0V).
If RESETSEL is LOW, RESET LOW sets all internal registers to code 000H (–10V).

FIGURE 3. Basic Dual-Supply Operation of the DAC7714.

DIGITAL INTERFACE Note that CS and CLK are combined with an OR gate and
Figure 4 and Table I provide the basic timing for the the output controls the serial-to-parallel shift register inter-
DAC7714. The interface consists of a serial clock (CLK), nal to the DAC7714 (see the block diagram on the front of
serial data (SDI), and a load DAC signal (LOADDACS). In this data sheet). These two inputs are completely inter-
addition, a chip select (CS) input is available to enable serial changeable. In addition, care must be taken with the state of
communication when there are multiple serial devices. An CLK when CS rises at the end of a serial transfer. If CLK is
asynchronous reset input (RESET) is provided to simplify LOW when CS rises, the OR gate will provide a rising edge
start-up conditions, periodic resets, or emergency resets to a to the shift register, shifting the internal data one additional
known state. bit. The result will be incorrect data and possible selection of
the wrong DAC.
The DAC code and address are provided via a 16-bit serial
interface (see Figure 4). The first two bits select the DAC If both CS and CLK are used, then CS should rise only when
register that will be updated when LOADDACS goes LOW CLK is HIGH. If not, then either CS or CLK can be used to
(see Table II). The next two bits are not used. The last 12 bits operate the shift register. See Table III for more information.
is the DAC code which is provided, most significant bit first.

13 DAC7714
 (MSB) (LSB)
SDI A1 A0 X X D11 D10 D9 D3 D2 D1 D0

CLK

tcss tCSH
CS

tLD1 tLD2
LOADDACS

tLDDW

tDS tDH

SDI

tCL tCH
CLK

tLDDW

LOADDACS
tS tS
1 LSB 1 LSB
VOUT ERROR BAND ERROR BAND

tRSTW
RESET

tRSSH

RESETSEL

FIGURE 4. DAC7714 Timing.

SYMBOL DESCRIPTION MIN TYP MAX UNITS STATE OF

SELECTED SELECTED
tDS Data Valid to CLK Rising 25 ns DAC DAC
tDH Data Held Valid after CLK Rises 20 ns A1 A0 LOADDACS RESET REGISTER REGISTER
tCH CLK HIGH 30 ns
tCL CLK LOW 50 ns L(1) L L H(2) A Transparent
tCSS CS LOW to CLK Rising 55 ns L H L H B Transparent
tCSH CLK HIGH to CS Rising 15 ns H L L H C Transparent
tLD1 LOADDACS HIGH to CLK Rising 40 ns H H L H D Transparent
tLD2 CLK Rising to LOADDACS LOW 15 ns X(3) X H H NONE (All Latched)
tLDDW LOADDACS LOW Time 45 ns X X X L ALL Reset(4)
tRSSH RESETSEL Valid to RESET LOW 25 ns NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care.
tRSTW RESET LOW Time 70 ns (4) Resets to either 000H or 800 H , per the RESETSEL state
tS Settling Time 10 µs (LOW = 000H, HIGH = 800H). When RESET rises, all registers that are in
their latched state retain the reset value.
TABLE I. Timing Specifications (TA = –40°C to +85°C).
TABLE II. Control Logic Truth Table.

DAC7714 14
 CS(1) CLK(1) LOADDACS RESET SERIAL SHIFT REGISTER LAYOUT
H(2) X(3) H H No Change
A precision analog component requires careful layout, ad-
L(4) L H H No Change
equate bypassing, and clean, well-regulated power supplies.
L ↑(5) H H Advanced One Bit As the DAC7714 offers single-supply operation, it will often
↑ L H H Advanced One Bit be used in close proximity with digital logic, microcontrollers,
H(6) X L(7) H No Change microprocessors, and digital signal processors. The more
H(6) X H L(8) No Change digital logic present in the design and the higher the switch-
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =
ing speed, the more difficult it will be to achieve good
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH performance from the converter.
value is suggested in order to avoid a “false clock” from advancing the shift
Because the DAC7714 has a single ground pin, all return
register and changing the shift register. (7) If data is clocked into the serial
register while LOADDACS is LOW, the selected DAC register will change as
currents, including digital and analog return currents, must
the shift register bits “flow” through A1 and A0. This will corrupt the data in flow through the GND pin. Ideally, GND would be con-
each DAC register that has been erroneously selected. (8) RESET LOW nected directly to an analog ground plane. This plane would
causes no change in the contents of the serial shift register. be separate from the ground connection for the digital
components until they were connected at the power entry
TABLE III. Serial Shift Register Truth Table.
point of the system.
The power applied to VCC (as well as VSS, if not grounded)
Digital Input Coding
should be well regulated and low noise. Switching power
The DAC7714 input data is in Straight Binary format. The supplies and DC/DC converters will often have high-fre-
output voltage is given by the following equation: quency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-fre-
(VREFH – VREFL ) • N quency spikes as their internal logic switches states. This
VOUT = VREFL + noise can easily couple into the DAC output voltage through
4096
various paths between the power connections and analog
output.
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.

15 DAC7714
 PACKAGE OPTION ADDENDUM
www.ti.com 3-Oct-2003

PACKAGING INFORMATION

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY
DAC7714U ACTIVE SOIC DW 16 48
DAC7714U/1K ACTIVE SOIC DW 16 1000
DAC7714UB ACTIVE SOIC DW 16 48
DAC7714UB/1K ACTIVE SOIC DW 16 1000

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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