®

DAC811

For most current data sheet and other product

information, visit www.burr-brown.com

Microprocessor-Compatible
12-BIT DIGITAL-TO-ANALOG CONVERTER

FEATURES Input gating logic is designed so that loading the last

nibble or byte of data can be accomplished simulta-
● SINGLE INTEGRATED CIRCUIT CHIP neously with the transfer of data (previously stored in
● MICROCOMPUTER INTERFACE: adjacent latches) from adjacent input latches to the
Double-Buffered Latch D/A latch. This feature avoids spurious analog output
● VOLTAGE OUTPUT: ±10V, ±5V, +10V values while using an interface technique that saves
computer instructions.
● MONOTONICITY GUARANTEED OVER
TEMPERATURE The DAC811 is laser trimmed at the wafer level and
is specified to ±1/4LSB maximum linearity error (B
● ±1/2LSB MAXIMUM NONLINEARITY OVER
and K grades) at 25°C and ±1/2LSB maximum over
TEMPERATURE
the temperature range. All grades are guaranteed mono-
● GUARANTEED SPECIFICATIONS AT ±12V tonic over the specification temperature range.
AND ±15V SUPPLIES
The DAC811 is available in six performance grades
● TTL/5V CMOS-COMPATIBLE LOGIC and three package types. DAC811J and K are speci-
INPUTS fied over the temperature ranges of 0°C to +70°C;
DAC811A and B are specified over –25°C to +85°C;
DESCRIPTION DAC811J and K are packaged in a reliable 28-pin
plastic DIP or plastic SO package, while DAC811A
The DAC811 is a complete, single-chip integrated- and B are available in a 28-pin 0.6" wide dual-inline
circuit, microprocessor-compatible, 12-bit digital-to- hermetically sealed ceramic side-brazed package (H
analog converter. The chip combines a precision volt- package).
age reference, microcomputer interface logic, and
double-buffered latch, in a 12-bit D/A converter with
4 MSBs 4 LSBs
a voltage output amplifier. Fast current switches and a
laser-trimmed thin-film resistor network provide a SJ
Input Latch Input Latch Input Latch
highly accurate and fast D/A converter.
RF 10V
Microcomputer interfacing is facilitated by a double- D/A Latch
buffered latch. The input latch is divided into three
4-bit nibbles to permit interfacing to 4-, 8-, 12-, or RF
12-Bit D/A Converter
16-bit buses and to handle right-or left-justified data.
The 12-bit data in the input latches is transferred to the RBPO VOUT
Voltage Reference BPO
D/A latch to hold the output value.

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®

© 1983 Burr-Brown Corporation PDS-503L Printed in U.S.A. April, 2000

1 DAC811
SBAS144
SPECIFICATIONS
At TA = +25°C. ±VCC = 12V or 15V, unless otherwise noted.

DAC811AH, JP, JU DAC811BH, KP, KU

PARAMETER MIN TYP MAX MIN TYP MAX UNITS

DIGITAL INPUT
Resolution 12 ✻ Bits
Codes(1) USB, BOB ✻
Digital Inputs Over Temperature Range(2)
VIH +2 +15 ✻ ✻ VDC
VIL 0 +0.8 ✻ ✻ VDC
IIH, VI = +2.7V +10 ✻ µA
IIL, VI = +0.4V ±20 ✻ µA
Digital Interface Timing Over Temperature Range
tWP, WR Pulse Width 50 ✻ ns
tAW1, NX and LDAC Valid to End of WR 50 ✻ ns
tDW, Data Valid to End of WR 80 ✻ ns
tDH, Data Valid Hold Time 0 ✻ ns
ACCURACY
Linearity Error ±1/4 ±1/2 ±1/8 ±1/4 LSB
Differential Linearity Error ±1/2 ±3/4 ±1/4 ±1/2 LSB
Gain Error(3) ±0.1 ±0.2 ✻ ✻ %
Offset Error(3, 4) ±0.05 ±0.15 ✻ ✻ % of FSR(5)
Monotonicity Guaranteed ✻
Power Supply Sensitivity: +VCC ±0.001 ±0.003 ✻ ✻ % of FSR/%VCC
–VCC ±0.002 ±0.006 ✻ ✻ % of FSR/%VCC
VDD ±0.0005 ±0.0015 ✻ ✻ % of FSR/%VDD

DRIFT (Over Specification Temperature Range)

Gain ±10 ±30 ±10 ±20 ppm/°C
Unipolar Offset ±5 ±10 ±5 ±7 ppm of FSR/°C
Bipolar Zero ±5 ±10 ±5 ±7 ppm of FSR/°C
Linearity Error Over Temperature Range ±1/2 ±3/4 ±1/4 ±1/2 LSB
Monotonicity Over Temperature Range Guaranteed ✻

SETTLING TIME(6) (to within ±0.01% of FSR of Final Value; 2kΩ load)
For Full Scale Range Change, 20V Range 3 4 ✻ ✻ µs
10V Range 3 4 ✻ ✻ µs
For 1LSB Change at Major Carry(7) 1 ✻ µs
Slew Rate(6) 8 12 ✻ ✻ V/µs
ANALOG OUTPUT
Voltage Range (±VCC = 15V)(8): Unipolar 0 to +10 ✻ V
Bipolar ±5, ±10 ✻ V
Output Current ±5 ✻ mA
Output Impedance (at DC) 0.2 ✻ Ω
Short Circuit to Common Duration Indefinite ✻

REFERENCE VOLTAGE
Voltage +6.2 +6.3 +6.4 ✻ ✻ ✻ V
Source Current Available for External Loads +2 ✻ mA
Temperature Coefficient ±10 ±30 ±10 ±20 ppm/°C
Short Circuit to Common Duration Indefinite ✻

POWER SUPPLY REQUIREMENTS

Voltage: +VCC +11.4 +15 +16.5 ✻ ✻ ✻ VDC
–VCC –11.4 –15 –16.5 ✻ ✻ ✻ VDC
VDD +4.5 +5 +5.5 ✻ ✻ ✻ VDC
Current (no load): +VCC +16 +25 ✻ ✻ mA
–VCC –23 –35 ✻ ✻ mA
VDD +8 +15 ✻ ✻ mA
Potential at DCOM with Respect to ACOM(9) ±0.5 ✻ V
Power Dissipation 625 800 ✻ ✻ mW
TEMPERATURE RANGE
Specification: J, K 0 +70 ✻ ✻ °C
A, B –25 +85 ✻ ✻ °C
R, S –65 +150 ✻ ✻ °C
°C
Storage: J, K –60 +100 ✻ ✻ °C
A, B, R, S –65 +150 ✻ ✻ °C

✻ Specification same as DAC811AH, JP, JU.

NOTES: (1) USB = unipolar straight binary; BOB = bipolar offset binary. (2) TTL, LSTTL and 54/74 HC compatible. (3) Adjustable to zero with external trim
potentiometer. (4) Error at input code 00016 for both unipolar and bipolar ranges. (5) FSR means full scale range and is 20V for the ±10V range. (6) Maximum
represents the 3σ limit. Not 100% tested for this parameter. (7) At the major carry, 7FF16 to 80016 and 80016 to 7FF16. (8) Minimum supply voltage required for ±10V
output swing is ±13.5V. Output swing for ±11.4V supplies is at least –8V to +8V. (9) The maximum voltage at which ACOM and DCOM may be separated without
affecting accuracy specifications.

DAC811 2
PIN DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS
PIN NAME FUNCTION +VCC ................................................................................................................................ 0 to +18V
–VCC to ACOM .......................................................................... 0 to –18V
1 +VDD Logic supply, +5V.
VDD to DCOM .............................................................................. 0 to +7V
2 WR Write, command signal to load latches. Logic low VDD to ACOM ...................................................................................... ±7V
loads latches. ACOM to DCOM .................................................................................. ±7V
3 LDAC Load D/A converter, enables WR to load the D/A Digital Inputs (Pins 2–14, 16–19) to DCOM ...................... –0.4V to +18V
latch. Logic low enables. External Voltage Applied to 10V Range Resistor ............................ ±12V
4 NA Nibble A, enables WR to load input latch A (the Ref Out ............................................................. Indefinite Short to ACOM
most significant nibble). Logic low enables. External Voltage Applied to DAC Output ................................ –5V to +5V
5 NB Nibble B, enables WR to load input latch B. Logic Power Dissipation ........................................................................ 1000mW
low enables. Lead Temperature (soldering, 10s) ............................................... +300°C
Max Junction Temperature ............................................................ +165°C
6 NC Nibble C, enables WR to load input latch C (the
Thermal Resistance, θJ-A: Plastic DIP and SOIC ....................... 100°C/W
least significant nibble). Logic low enables.
Ceramic DIP .................................................................................. 65°C/W
7 D11 Data bit 12, MSB, positive true.
8 D10 Data bit 11. NOTE: Stresses above those listed above may cause permanent damage to
the device. Exposure to absolute maximum conditions for extended periods
9 D9 Data bit 10.
may affect device reliability.
10 D8 Data bit 9.
11 D7 Data bit 8.
12
13
D6
D5
Data bit 7.
Data bit 6.
ELECTROSTATIC
14 D4 Data bit 5. DISCHARGE SENSITIVITY
15 DCOM Digital common, VDD supply return.
16 D0 Data bit 1, LSB. This integrated circuit can be damaged by ESD. Burr-Brown
17 D1 Data bit 2. recommends that all integrated circuits be handled with
18 D2 Data bit 3. appropriate precautions. Failure to observe proper handling
19 D3 Data bit 4. and installation procedures can cause damage.
20 +VCC Analog supply input, +15V or +12V.
21 –VCC Analog supply input, –15V or –12V. ESD damage can range from subtle performance degradation
22 Gain Adj To externally adjust gain. to complete device failure. Precision integrated circuits may
23 ACOM Analog common, ±VCC supply return. be more susceptible to damage because very small parametric
24 VOUT D/A converter voltage output. changes could cause the device not to meet its published
25 10V Range Connect to pin 24 for 10V range.
specifications.
26 SJ Summing junction of output amplifier.
27 BPO Bipolar offset. Connect to pin 26 for bipolar
operation.
28 Ref Out 6.3V reference output.

PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE DIFFERENTIAL PACKAGE SPECIFICATION
ACCURACY LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE NUMBER RANGE NUMBER(1) MEDIA

DAC811AH ±1/2 LSB 3/4 CERDIP-28 149 –25°C to +85°C DAC811AH Rails
DAC811JP ±1/2 LSB 3/4 DIP-28 215 0°C to +70°C DAC811JP Rails
DAC811JU ±1/2 LSB 3/4 SO-28 217 0°C to +70°C DAC811JU Rails
" " " " " " DAC811JU/1K Tape and Reel
DAC811KP ±1/4 LSB 1/2 DIP-28 215 0°C to +70°C DAC811KP Rails
DAC811KU ±1/4 LSB 1/2 SO-28 217 0°C to +70°C DAC811KU Rails

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC811JU/1K” will get a single 1000-piece Tape and Reel.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

3 DAC811
TIMING DIAGRAMS

Write Cycle #2
Write Cycle #1
Load second rank from first rank: NA , NB , N C = 1
Load first rank from Data Bus: LDAC = 1
tAW
tAW
LDAC
N A , NB , N C
tWP
tDW
WR
DB11 –DB0
tSET
tDH
tWP
WR ±1/2LSB

DISCUSSION OF DRIFT
Gain drift is a measure of the change in the full scale range
SPECIFICATIONS (FSR) output over the specification temperature range. Drift is
expressed in parts per million per degree centigrade
INPUT CODES
(ppm/°C). Gain drift is established by testing the full scale
The DAC811 accepts positive-true binary input codes. range value (e.g., +FS minus –FS) at high temperature, +25°C,
DAC811 may be connected by the user for any one of the and low temperature, calculating the error with respect to the
following codes: USB (unipolar straight binary), BOB (bi- +25°C value, and dividing by the temperature change.
polar offset binary) or, using an external inverter on the
MSB line, BTC (binary two’s complement). See Table I. Unipolar offset drift is a measure of the change in output
with all 0s on the input over the specification temperature
range. Offset is measured at high temperature, +25°C, and
DIGITAL INPUT ANALOG OUTPUT
low temperature. The offset drift is the maximum change in
USB BOB BTC(1) offset referred to the +25°C value, divided by the tempera-
Unipolar Bipolar Binary
Straight Offset Two’s ture change. It is expressed in parts per million of full scale
MSB LSB
Binary Binary Complement range per degree centigrade (ppm of FSR/°C).
↓ ↓
111111111111 + Full Scale + Full Scale –1LSB Bipolar zero drift is measured at a digital input of 80016, the
100000000000 + 1/2 Full Scale Zero – Full Scale
011111111111 + 1/2 Full Scale – 1LSB –1LSB + Full Scale code that gives zero volts output for bipolar operation.
000000000000 Zero – Full Scale Zero

NOTE: (1) Invert MSB of the BOB code with external inverter to obtain BTC code. SETTLING TIME
TABLE I. Digital Input Codes. Settling time is the total time (including slew time) for the
output to settle within an error band around its final value
LINEARITY ERROR after a change in input. Three settling times are specified to
±0.01% of full scale range (FSR): two for maximum full
Linearity error as used in D/A converter specifications by
scale range changes of 20V and 10V, and one for a 1LSB
Burr-Brown is the deviation of the analog output from a
change. The 1LSB change is measured at the major carry
straight line drawn between the end points (inputs all 1s and
(7FF16 to 80016 and 80016 to 7FF16), the input transition at
all 0s). The DAC811 linearity error is specified at ±1/4LSB
which worst-case settling time occurs.
(max) at +25°C for B and K grades, and ±1/2LSB (max) for
A and J grades.
REFERENCE SUPPLY
DIFFERENTIAL LINEARITY ERROR DAC811 contains an on-chip 6.3V reference. This voltage
Differential linearity error (DLE) is the deviation from a (pin 28) has a tolerance of ±0.1V. The reference output may
1LSB output change from one adjacent state to the next. A be used to drive external loads, sourcing at least 2mA. This
DLE specification of 1/2LSB means that the output step size current should be constant for best performance of the D/A
can range from 1/2LSB to 3/2LSB when the input changes converter.
from one state to the next. Monotonicity requires that DLE
be less than 1LSB over the temperature range of interest. POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
MONOTONICITY power supply change on the D/A converter output. It is
defined as a percent of FSR output change per percent of
A D/A converter is monotonic if the output either increases
change in either the positive, negative, or logic supply
or remains the same for increasing digital inputs. All grades
voltages about the nominal voltages. Figure 1 shows typical
of DAC811 are monotonic over their specification tempera-
power supply rejection versus power supply ripple frequency.
ture range.
®

DAC811 4
 1
The D/A latch is controlled by LDAC and WR. LDAC and
WR are internally NORed so that the latches transmit data to

Change of Power Supply Voltage

the D/A switches when both LDAC and WR are at logic 0.
Percent of FSR per Percent of
–VCC
0.1 When either LDAC or WR are at logic 1, the data is latched
in the D/A latch and held until LDAC and WR go to logic 0.
V DD All latches are level-triggered. Data present when the con-
0.01
trol signals are logic 0 will enter the latch. When any one of
the control signals returns to logic 1, the data is latched.
+VCC
0.001 Table II is a truth table for all latches.

WR NA NB NC LDAC OPERATION
0.0001
10 100 1k 10k 100k 1M 1 X X X X No operation
Frequency (Hz) 0 0 1 1 1 Enables input latch 4MSBs
0 1 0 1 1 Enables input latch 4 middle bits
0 1 1 0 1 Enables input latch 4LSBs
FIGURE 1. Power Supply Rejection vs Power Supply Ripple 0 1 1 1 0 Loads D/A latch from input latches
Frequency. 0 0 0 0 0 Makes all latches transparent
“X” = Don’t care.

OPERATION TABLE II. DAC813 Interface Logic Truth Table.

DAC811 is a complete single IC chip 12-bit D/A converter.
The chip contains a 12-bit D/A converter, voltage reference, GAIN AND OFFSET ADJUSTMENTS
output amplifier, and microcomputer-compatible input logic Figures 3 and 4 illustrate the relationship of offset and gain
as shown in Figure 2. adjustments to unipolar and bipolar D/A converter output.

INTERFACE LOGIC OFFSET ADJUSTMENT

Input latches A, B, and C hold data temporarily while a For unipolar (USB) configurations, apply the digital input
complete 12-bit word is assembled before loading into the code that should produce zero voltage output, and adjust the
D/A register. This double-buffered organization prevents the offset potentiometer for zero output. For bipolar (BOB,
generation of spurious analog output values. Each register is BTC) configurations, apply the digital input code that should
independently addressable. produce the maximum negative output voltage and adjust
These input latches are controlled by NA, NB, NC, and WR. the offset potentiometer for minus full scale voltage. Ex-
NA, NB, and NC are internally NORed with WR so that the ample: If the full scale range is connected for 20V, the
input latches transmit data when both NA (or NB, NC ) and maximum negative output voltage is –10V. See Table III for
WR are at logic 0. When either NA, (NB, NC ) or WR go to corresponding codes.
logic 1, the input data is latched into the input registers and
held until both NA (or NB, NC ) and WR go to logic 0.

MSB D11 D8 D7 D4 D3 D0 LSB

7 8 9 10 11 12 13 14 19 18 17 16

WR 2 RBPO
4-Bit Latch, A 4-Bit Latch, B 4-Bit Latch, C 27 BPO
NA 4

NB 5 26 SJ
RF
NC 6 10V
25
Range
LDAC 3 12-Bit D/A Latch
RF

12-Bit D/A Converter

24 VOUT

Reference

23 ACOM
Ref Out 28

FIGURE 2. DAC811 Block Diagram.

5 DAC811
 ±12V OPERATION
The DAC811 is fully specified for operation on ±12V power
+ Full Scale Range of
Gain Adjust supplies. However, in order for the output to swing to ±10V,
the power supplies must be ±13.5V or greater. When oper-
1LSB
ating with ±12VB supplies, the output swing should be
Analog Output

Full Scale Range

restricted to ±8V in order to meet specifications.

Gain Adjust LOGIC INPUT COMPATIBILITY
Rotates the Line
The DAC811 digital inputs are TTL, LSTTL, and 54/74HC
CMOS-compatible over the operating range of VDD. The
All Bits
Range of
Logic 0
input switching threshold remains at the TLL threshold over
Offset Adj. All Bits
Logic 1 the supply range.
The logic input current over temperature is low enough to
permit driving the DAC811 directly from the outputs of
Digital Input 4000B and 54/74C CMOS devices.
Offset Adjust Translates the Line
Resistors of 47Ω should be placed in series with D0 through
D11, WR, NA, NB, NC and LDAC if edges are <10ns or if
FIGURE 3. Relationship of Offset and Gain Adjustments
the logic input is driven below ground by undershoot.
for a Unipolar D/A Converter.

INSTALLATION
+ Full Scale
POWER SUPPLY CONNECTIONS
1LSB For optimum performance and noise rejection, power supply
Range of decoupling capacitors should be added as shown in Figure 5.
Gain Adjust
All Bits Full Scale
Range Gain Adjust These capacitors (1µF tantalum recommended) should be
Logic 0
Analog Output

Rotates the Line located close to the DAC811.

Bipolar V
Offset MSB on All All Bits
Others Off Logic 1 Connect for
Range of VDD Bipolar Operation
1 V DD 28
Offset Adjust
–VCC
– Full Scale 2 BPO 27
Offset Adj. 1MΩ
Translates Summing 10k Ω to
1µF 3 26
the Line Junction 100kΩ
Digital Input
≈ ±0.4% 4 25

5 VOUT 24
FIGURE 4. Relationship of Offset and Gain Adjustments +VCC
for a Bipolar D/A Converter. 6 ACOM 23
3.9MΩ 10k Ω to
7 Gain Adjust 22 100kΩ
ANALOG OUTPUT 8 –VCC 21 –VCC
DIGITAL INPUT 0 to +10V ±5V ±10V +VCC +VCC
9 20
MSB LSB
↓ ↓ 10 19
111111111111 +9.9976V +4.9976V +9.9951V 0.0022µF
11 18
100000000000 +5V 0V 0V
011111111111 +4.9976V –0.0024V –0.0049V 12 17 1µF
000000000000 0V –5V –10V
LSB 2.4mV 2.44mV 4.88mV 13 16
1µF
14 DCOM 15
TABLE III. Digital Input/Analog Output.

GAIN ADJUSTMENT
For either unipolar or bipolar configurations, apply the
digital input that should give the maximum positive voltage
FIGURE 5. Power Supply, Gain, and Offset Potentiometer
output. Adjust the gain potentiometer for this positive full
Connections.
scale voltage. See Table III for positive full scale voltages.

DAC811 6
DAC811 features separate digital and analog power supply 5.36kΩ
returns to permit optimum connections for low noise and From Voltage
27 Bipolar Offset
Reference
high speed performance. The analog common (pin 23) and
26 Summing Junction
digital common (pin 15) should be connected together at one 4.26kΩ
point. Separate returns minimize current flow in low level 25 10V Range
signal paths if properly connected. Logic return currents are From D/A 4.26kΩ
not added into the analog signal return path. A ±0.5V Converter
24 VOUT
difference between ACOM and DCOM is permitted for
specified operation. High frequency noise on DCOM with
respect to ACOM may permit noise to be coupled through to 23 Analog Common

the analog output; therefore, some caution is required in

applying these common connections. FIGURE 7. Output Amplifier Voltage Range Scaling Circuit.
The Analog Common is the high quality return for the D/A
converter and should be connected directly to the analog OUTPUT DIGITAL CONNECT CONNECT
reference point of the system. The load driven by the output RANGE INPUT CODES PIN 25 TO PIN 27 TO

amplifier should be returned to the Analog Common. 0 to +10V USB 24 23

±5 BOB or BTC 24 26
±10V BOB or BTC NC 26
EXTERNAL OFFSET AND GAIN ADJUSTMENT
TABLE IV. Output Range Connections.
Offset and Gain may be trimmed by installing external
Offset and Gain potentiometers. Connect these potentiom-
eters as shown in Figure 5. TCR of the potentiometers
should be 100ppm/°C or less. The 1MΩ and 3.9MΩ resis- APPLICATIONS
tors (20% carbon or better) should be located close to the
DAC811 to prevent noise pickup. If it is not convenient to MICROCOMPUTER BUS INTERFACING
use these high value resistors, an equivalent “T” network, as The DAC811 interface logic allows easy interface to micro-
shown in Figure 6, may be substituted in each case. The computer bus structures. The control signal WR is derived
Gain Adjust (pin 22) is a high impedance point and a from external device select logic and the I/O Write or
0.001µF to 0.01µF ceramic capacitor should be connected Memory Write (depending upon the system design) signals
from this pin to Analog Common to reduce noise pickup in from the microcomputer.
all applications, including those not employing external gain The latch enable lines NA, NB, NC and LDAC determine
adjustment. Excessive capacitance on the Gain Adjust or which of the latches are enabled. It is permissible to enable
Offset Adjust pin may affect slew rate and settling time. two or more latches simultaneously, as shown in some of the
following examples.
The double-buffered latch permits data to be loaded into the
1MΩ 100kΩ 100kΩ input latches of several DAC811s and later strobed into the
D/A latch of all D/As, simultaneously updating all analog
12kΩ outputs. All the interface schemes shown below use a base
address decoder. If blocks of memory are used, the base
3.9MΩ 180kΩ 180kΩ address decoder can be simplified or eliminated altogether.
For instance, if half the memory space is unused, address
10kΩ line A15 of the microcomputer can be used as the chip select
control.

4-BIT INTERFACE
FIGURE 6. Equivalent Resistances.
An interface to a 4-bit microcomputer is shown in Figure 8.
Each DAC811 occupies four address locations. A 74LS139
OUTPUT RANGE CONNECTIONS
provides the two-to-four decoder and selects it with the base
Internal scaling resistors provided in the DAC811 may be address. Memory Write (WR) of the microcomputer is
connected to produce bipolar output voltage ranges of ±10V connected directly to the WR pin of the DAC811. An 8205
and ±5V or a unipolar output voltage range of 0 to +10V. decoder is an alternative to the 74LS139.
The 20V range (±10V bipolar range) is internally connected.
Refer to Figure 7. Connections for the output ranges are
listed in Table IV.

7 DAC811
8-BIT INTERFACE
The control logic of DAC811 permits interfacing to right- 16 D0
DB0
justified data formats, as illustrated in Figure 9. When a 10 D8
12-bit D/A converter is loaded from an 8-bit bus, two bytes 17 D1
of data are required. Figures 10 and 11 show an addressing DB1
9 D9
scheme for right-justified and left-justified data respectively.
18 D2
The base address is decoded from the high-order address DB2
bits. A0 and A1 address the appropriate latches. Note that 8 D10

adjacent addresses are used. For the right-justified case, 19 D3

DB3
X1016 loads the 8LSBs, and X0116 loads the 4MSBs and 7 D11
simultaneously transfers input latch data to the D/A latch. DB4 14 D4

Microcomputer
Addresses X0016 and X1116 are not used.

DAC811
DB5 13 D5
Left-justified data is handled in a similar manner, shown in DB6 12 D6
Figure 11. The DAC811 still occupies two adjacent loca-
DB7 11 D7
tions in the microcomputer's memory map.
WR

2 WR
A15 Base
16 D0 Address
A2 Decoder
DB0 14 D4 CS LDAC
3
A1
10 D8 4 NA
17 D1 5 NB
A0
DB1 13 D5 6 NC
9 D9
18 D2
FIGURE 10. Right-Justified Data Bus Interface.
DB2 12 D6

8 D10
Microcomputer

19 D3
DAC811

14 D4
DB3 11 D7 DB0
13 D5
7 D11
12 D6
WR 2 WR DB1
11 D7
AN Base
Address 10 D8
CS
A2 Decoder DB2
(Chip 16 D0
Select)
9 D9
1 7 DB3
EN Y3 3 LDAC 17 D1
A1 3 A1 6
Y2 4 NA DB4 8 D10
Microcomputer

A0 2 A0 5
Y1 5 NB DAC811
DB5 18 D2
1/2 4
Y0 6 NC
74LS139 DB6 7 D11

DB7 19 D3
FIGURE 8. Addressing and Control for 4-Bit Microcom-
puter Interface. WR

2 WR
A15 Base
Address
X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 Decoder
CS LDAC
3
a. Right-Justified A1 4 NA

5 NB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
A0 6 NC

b. Left-Justified

FIGURE 11. Left-Justified Data Bus Interface.

FIGURE 9. 12-Bit Data Format for 8-Bit Systems.

DAC811 8
INTERFACING MULTIPLE DAC811s eight address spaces for other uses. Incorporate A3 into the
IN 8-BIT SYSTEMS base address decoder, remove the inverter, connect the
Many applications, such as automatic test systems, require common LDAC line to NC of D/A #4, and connect D1 of the
that the outputs of several D/A converters be updated simul- 74LS138 to +5V.
taneously. The interface shown in Figure 12 uses a 74LS138
decoder to decode a set of eight adjacent addresses, to load 12- AND 16-BIT MICROCOMPUTER INTERFACE
the input latches of four DAC811s. The example shows a For this application, the input latch enable lines, NA, NB and
right-justified data format. NC, are tied low, causing the latches to be transparent. The
A ninth address using A3 causes all DAC811s to be updated D/A latch, and therefore DAC811, is selected by the address
simultaneously. If a particular DAC811 is always loaded decoder and strobed by WR.
last—for instance, D/A #4—A3 is not needed, thus saving

WR WR
A15 LDAC
Base DAC811
CS
Address NC
(1)
A4 Decoder NB
ADDRESS BUS
NA A3 A2 A1 A0 OPERATION

A3 0 0 0 0 Load 8 LSB – D/A #1

WR 0 0 0 1 Load 4 MSB – D/A #1
74LS138
LDAC 0 0 1 0 Load 8 MSB – D/A #2
Microcomputer

4 15 DAC811
G2A NC 0 0 1 1 Load 4 MSB – D/A #2
14 (2)
5 Y0 NB
G2B 13 0 1 0 0 Load 8 MSB – D/A #3
Y1 NA
12 0 1 0 1 Load 4 MSB – D/A #3
G1 Y2
6 0 1 1 0 Load 8 MSB – D/A #4
Y3 11
0 1 1 1 Load 4 MSB – D/A #4
Y4 10 WR
Y5 LDAC 1 X X X Load D/A Latch—All D/A
3 DAC811
A2 C NC
9 (4)
2 NB
A1 B Y6
1 7
A0 A Y7 NA

FIGURE 12. Interfacing Multiple DAC811s to an 8-Bit Bus.

9 DAC811
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DAC811BH ACTIVE CDIP SB JD 28 1 RoHS & Green AU N / A for Pkg Type -25 to 85 DAC811BH

DAC811JU ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 DAC811JU

DAC811JU/1K ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 DAC811JU

DAC811JUG4 ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 DAC811JU

DAC811KU ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 DAC811KU

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC811JU/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC811JU/1K SOIC DW 28 1000 367.0 367.0 55.0

Pack Materials-Page 2
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