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CMOS Logic Design Essentials

This document discusses CMOS logic gates and their design. It notes that static CMOS gates must be inverting by design. Non-inverting gates can be built by combining multiple inverting gates. Tristate buffers allow an output to be left floating when enabled, implemented using a transmission gate with an enable input controlling the transistors.

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Carlos Saavedra
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62 views1 page

CMOS Logic Design Essentials

This document discusses CMOS logic gates and their design. It notes that static CMOS gates must be inverting by design. Non-inverting gates can be built by combining multiple inverting gates. Tristate buffers allow an output to be left floating when enabled, implemented using a transmission gate with an enable input controlling the transistors.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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14 Chapter 1 Introduction

A consequence of the design of static CMOS gates is that they must be inverting.
BAD
The nMOS pull-down network turns ON when inputs are 1, leading to 0 at the output.
VDD
We might be tempted to turn the transistors upside down to build a noninverting gate. For
example, Figure 1.22 shows a noninverting buffer. Unfortunately, now both the nMOS
A Y and pMOS transistors produce degraded outputs, so the technique should be avoided.
Instead, we can build noninverting functions from multiple stages of inverting gates. Fig-
GND ure 1.23 shows several ways to build a 4-input AND gate from two levels of inverting
static CMOS gates. Each design has different speed, size, and power trade-offs.
Similarly, the compound gate of Figure 1.18 could be built with two AND gates, an
A Y
OR gate, and an inverter. The AND and OR gates in turn could be constructed from
NAND/NOR gates and inverters, as shown in Figure 1.24, using a total of 20 transistors,
FIGURE 1.22 as compared to eight in Figure 1.18. Good CMOS logic designers exploit the efficiencies
Bad noninverting buffer of compound gates rather than using large numbers of AND/OR gates.

A
4 2
B
4 2 2 Y
C
4 2
D OR
AND
FIGURE 1.24 Inefficient discrete gate implementation of AOI22
with transistor counts indicated

FIGURE 1.23 Various implementations


of a CMOS 4-input AND gate

EN
1.4.7 Tristates
A Y
Figure 1.25 shows symbols for a tristate buffer. When the enable input EN is 1, the output
EN Y equals the input A, just as in an ordinary buffer. When the enable is 0, Y is left floating (a
‘Z’ value). This is summarized in Table 1.5. Sometimes both true and complementary
A Y enable signals EN and EN are drawn explicitly, while sometimes only EN is shown.
EN TABLE 1.5 Truth table for tristate
FIGURE 1.25 EN / EN A Y
Tristate buffer
symbol 0/1 0 Z
0/1 1 Z
1/0 0 0
EN
1/0 1 1
A Y
The transmission gate in Figure 1.26 has the same truth table as a tristate buffer. It
EN only requires two transistors but it is a nonrestoring circuit. If the input is noisy or other-
FIGURE 1.26 wise degraded, the output will receive the same noise. We will see in Section 4.4.2 that the
Transmission gate delay of a series of nonrestoring gates increases rapidly with the number of gates.

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