0% found this document useful (0 votes)
26 views19 pages

SN54F240, SN74F240 Octal Buffers/Drivers With 3-State Outputs

Buffer for the 74F series of 5v Bipolar logic

Uploaded by

rectibeira
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
26 views19 pages

SN54F240, SN74F240 Octal Buffers/Drivers With 3-State Outputs

Buffer for the 74F series of 5v Bipolar logic

Uploaded by

rectibeira
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 19

SN54F240, SN74F240

OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDFS061A – D2932, MARCH 1987 – REVISED OCTOBER 1993

• 3-State Outputs Drive Bus Lines or Buffer SN54F240 . . . J PACKAGE


Memory Address Registers SN74F240 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline (SOIC) and Shrink 1OE 1 20 VCC
Small-Outline (SSOP) Packages, Ceramic 1A1 2 19 2OE
Chip Carriers, and Plastic and Ceramic 2Y4 3 18 1Y1
DIPs 1A2 4 17 2A4
2Y3 5 16 1Y2
description 1A3 6 15 2A3
These octal buffers and line drivers are designed 2Y2 7 14 1Y3
specifically to improve both the performance and 1A4 8 13 2A2
density of 3-state memory address drivers, clock 2Y1 9 12 1Y4
drivers, and bus-oriented receivers and GND 10 11 2A1
transmitters. Taken together with the ′F241 and
′F244, these devices provide the choice of SN54F240 . . . FK PACKAGE
selected combinations of inverting and (TOP VIEW)
noninverting outputs, symmetrical OE (active-low

1OE

2OE
VCC
2Y4
1A1
output-enable) inputs, and complementary OE
and OE inputs.
3 2 1 20 19
The ′F240 is organized as two 4-bit buffers/line 1A2 4 18 1Y1
drivers with separate output enable (OE) inputs. 2Y3 5 17 2A4
When OE is low, the device passes data from the 1A3 6 16 1Y2
A inputs to the Y outputs. When OE is high, the 2Y2 7 15 2A3
outputs are in the high-impedance state. 1A4 8 14 1Y3
9 10 11 12 13
The SN74F240 is available in TI’s shrink

2Y1

2A1
1Y4
2A2
GND
small-outline package (DB), which provides the
same I/O pin count and functionality of standard
small-outline packages in less than half the
printed-circuit-board area.
The SN54F240 is characterized for operation over
the full military temperature range of – 55°C to
125°C. The SN74F240 is characterized for
operation from 0°C to 70°C.

FUNCTION TABLE
(each buffer)
INPUTS OUTPUT
OE A Y
L H L
L L H
H X Z

PRODUCTION DATA information is current as of publication date. Copyright  1993, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1


SN54F240, SN74F240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDFS061A – D2932, MARCH 1987 – REVISED OCTOBER 1993

logic symbol† logic diagram (positive logic)


1
1 1OE
1OE EN

2 18 2 18
1A1 1Y1 1A1 1Y1
4 16
1A2 1Y2
6 14 16
1A3 1Y3 4 1Y2
1A2
8 12
1A4 1Y4
14
6
1A3 1Y3
19
2OE EN
8 12
1A4 1Y4
11 9
2A1 2Y1
13 7
2A2 2Y2
15 5 19
2A3 2Y3 2OE
17 3
2A4 2Y4
11 9
† This symbol is in accordance with ANSI/IEEE Std 91-1984 2A1 2Y1
and IEC Publication 617-12.
13 7
2A2 2Y2

15 5
2A3 2Y3

17 3
2A4 2Y4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA
Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC
Current into any output in the low state: SN54F240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74F240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Operating free-air temperature range: SN54F240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74F240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.

2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN54F240, SN74F240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDFS061A – D2932, MARCH 1987 – REVISED OCTOBER 1993

recommended operating conditions


SN54F240 SN74F240
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IIK Input clamp current – 18 – 18 mA
IOH High-level output current – 12 – 15 mA
IOL Low-level output current 48 64 mA
TA Operating free-air temperature – 55 125 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless


otherwise noted)
SN54F240 SN74F240
PARAMETER TEST CONDITIONS UNIT
MIN TYP† MAX MIN TYP† MAX
VIK VCC = 4.5 V, II = – 18 mA – 1.2 – 1.2 V
IOH = – 3 mA 2.4 3.3 2.4 3.3
VCC = 4.5 V IOH = – 12 mA 2 3.2
VOH V
IOH = – 15 mA 2 3.1
VCC = 4.75 V, IOH = – 3 mA 2.7
IOL = 48 mA 0.38 0.55
VOL VCC = 4
4.5
5V V
IOL = 64 mA 0.42 0.55
IOZH VCC = 5.5 V, VO = 2.7 V 50 50 µA
IOZL VCC = 5.5 V, VO = 0.5 V – 50 – 50 µA
II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.5 V –1 –1 mA
IOS‡ VCC = 5.5 V, VO = 0 – 100 – 225 – 100 – 225 mA
Outputs high 19 29 19 29
ICC VCC = 5.5 V Outputs low 50 75 50 75 mA
Outputs disabled 42 63 42 63
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3


SN54F240, SN74F240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDFS061A – D2932, MARCH 1987 – REVISED OCTOBER 1993

switching characteristics (see Note 2)


VCC = 5 V, VCC = 4.5 V to 5.5 V,
CL = 50 pF, CL = 50 pF,
FROM TO RL = 500 Ω, RL = 500 Ω,
PARAMETER
(INPUT) (OUTPUT) TA = 25°C TA = MIN to MAX† UNIT
′F240 SN54F240 SN74F240
MIN TYP MAX MIN MAX MIN MAX
tPLH 2.2 4.7 7 2.2 9 2.2 8
Any A Y ns
tPHL 1.2 3.1 4.7 1.2 6 1.2 5.7
tPZH 1.2 3.1 5.3 1.2 6.7 1.2 6.1
OE Y ns
tPZL 3.2 6.5 9 3.2 10.5 3.2 10
tPHZ 1.2 3.6 5.3 1.2 6.5 1.2 6.3
OE Y ns
tPLZ 1.2 5.6 8 1.2 12.5 1.2 9.5
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and waveforms are shown in Section 1.

2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9758501Q2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9758501Q2A
SNJ54F
240FK
5962-9758501QRA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9758501QR Samples
& Green A
SNJ54F240J
5962-9758501QSA ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9758501QS Samples
& Green A
SNJ54F240W
JM38510/33201B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 33201B2A
JM38510/33201BRA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 33201BRA
JM38510/33201BSA ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 33201BSA
M38510/33201B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 33201B2A
M38510/33201BRA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 33201BRA
M38510/33201BSA ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 33201BSA
SN54F240J ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54F240J Samples
& Green
SN74F240DW LIFEBUY SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 F240
SN74F240DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 F240 Samples

SN74F240N ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type 0 to 70 SN74F240N Samples
Non-Green
SN74F240NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74F240 Samples

SNJ54F240FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9758501Q2A
SNJ54F
240FK

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2023

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SNJ54F240J ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9758501QR Samples
& Green A
SNJ54F240J
SNJ54F240W ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9758501QS Samples
& Green A
SNJ54F240W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2023

OTHER QUALIFIED VERSIONS OF SN54F240, SN74F240 :

• Catalog : SN74F240
• Military : SN54F240

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product


• Military - QML certified for Military and Defense Applications

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74F240DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74F240NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74F240DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74F240NSR SO NS 20 2000 367.0 367.0 45.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9758501Q2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9758501QSA W CFP 20 1 506.98 26.16 6220 NA
JM38510/33201B2A FK LCCC 20 1 506.98 12.06 2030 NA
JM38510/33201BSA W CFP 20 1 506.98 26.16 6220 NA
M38510/33201B2A FK LCCC 20 1 506.98 12.06 2030 NA
M38510/33201BSA W CFP 20 1 506.98 26.16 6220 NA
SN74F240DW DW SOIC 20 25 507 12.83 5080 6.6
SN74F240N N PDIP 20 20 506 13.97 11230 4.32
SNJ54F240FK FK LCCC 20 1 506.98 12.06 2030 NA
SNJ54F240W W CFP 20 1 506.98 26.16 6220 NA

Pack Materials-Page 3
GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE


TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE


SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK


METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN


ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS


4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

You might also like