ae Short Questions’ \ What ave athe ‘dyausbatls ol Binary, wegnied “vesictor . | GQ) The ck Neqyuives side ange \ 9. YeciSors Eps + fer 8-Git daha, tne Verve mrequve Ov" AR O*R, Late. Suh a unde Vasiety of) Yeitors yalues are Vet desi vable |W) Fatai Caton oy Tord yaues “ressins on chip O15 diicatt QW todd DAC. S | These dvavs backs 2) Lihat “iS Dla 2 Name te aMiteaad 4ypesseye OPCS 2 axe mnev come Th the = The creat thal Convert pigital to Analog (dla) * Caned + OIA Conniecters } | | | | ave! The piffer t4y~2s of pacs | Vv) Binavy weighted Resistoy ‘DAC | a Wi) Q~2R Ladden DAC. DH tise oak ditferert tees ahaa Oe uae The diffevert tapes el Alp Convertevs ewe» GO) dived stupe ADC W) Dat egrated ay pe ADC G) Which type oy A0¢ <6 the fastest 7 Why? The Flash Ade Vs the Fastest. ° Recaute fash ADE Used Comparctoys, OMe ev Voltase Step, and a Sting eh Yeusdtise. A G-Lit Ade wit Nave Le compavatos yan @- bit ADE LIN have 256 ComparaterE ___ Short Questions: \. What axe the ‘cdyauslectes oly Binary weghied ~*esicter . aly 4 YesiSers. Q) The Ck Yeqtivey a Uside Yange 1 Err «fer 8-Git doba, Ane Verirwous mpequvrer) one TROP, afm. Sah a ude Vanety ef Yeristors values are vet desi xable. BW). Ea eden stp lenge Utes resis Cony ais difficult the Jie ne Se anne Rag Ladder DAC 2) Wdhad iS dla 2 Nate tre ditlaad apes ah oACs ) ay qe Crest chen Contes Crimes rsd (ole) | Caned - Dia Conectes] The Different types oly pac’ AY Binary Weighted Resistor DAC: Wy) Q-2e Ladder DAC. Lis oak ote tUCes Ay AE Nee The differed per ol Alp Converts ceve GC) pnect type ADC W) Dat equated type ADC axe: v9, 9) Which tupe \ ADCS ae fastest 4 Why ? The Flash Adc is the Fastest. © > Because flash Ade User comparadoys, OMe pey Voltase (tep, and & Sting * Yeusnese., A G-bit Ade will Nave Lb comparators pan @- BA ADC Lolll have 156 Comparater.Digit ELECTRONICS. — Question) BANK WITH _ ANS WERS | | PoRT-A line. [unit -V] 6 Define the following terms as yeloted to DAC? Ab Lineostity = Lineoxtity of Dac & 4 measure of fhe precigon q conversfon. Jn an ideal DAC, qual incremeo’s | fin the digftal input Conespond fo equal Tncremenks in the | analey output Value « i} Resoludion= The Aaalucton ot precgion a Such a Dac + is defined os the Smallest output increment posible divided by the difference blur the maximum and minimum output Values. % boffoe FAN-IN and FAN-OUT? | at) EON-IN faith Aopers 40 the maximum noo input Tynes | that feed the inp equations of logic Gl. The term that depfines the maximum no: of digital inputs that a Single logic gate (oh accept | EPALOUTs Fan oud {5 the no-q gate Input driven by the oudput of anotht single logic Gate. % What do you mean by pantization enor fh an POC? fe Quantizoton error fs the difleren@ Yu Me analog Sigtel and the Closettavailable digital Value at | tue at Gach | fastant fom the AlD Converter. rs pas= 4) bhat ave the limitations of weighted! estes type PAC M The Uimbedtion’ of lel ‘ghted Sesste, type ppc are t 4. Th sequites a very prectse Value of Sexfotots and a loge | gap blid LSB and MSB esr shs Values - 4. Tt betames tmpactical 16 highes ves Drteand fs Suftable 7 lex Serolutten DAC. 3. The Sfubilfty of the device f Aerishs el atfeded are by empercature vadatons - loy JJhat {6 Monotonocity and off set E03? a Converter Such AY Monotonédly- tt means the ouput Of as ppt always Ancyeaset decreases utth the taput and never Acwerses drvectren: olties EMS + OFFSet Means fhe difference blu’ the Signe! that fs given and the Sonal thab fe Aecolved by q System & a devile - POREB . 1) @ Mhet are the clraswbacks of weighted Yesistos | type Dac? 4: The drawbacks of welghted pests type DAC ave : “he The Grunt Meqiter a wide Yarge Cf HOHRStO32.. | Q. fabsticadton of large Value “neststor on clip hs difpicult 3. power Ascipatten ¢ binary Likighted seststd Orcas Pa | epen dent and fs4- Th becomer impaachial 16 higher order Dpcs ni “fui 78 lew reroluton pecs Z 5. The Llabilihy of the aevic te seiittor dependent and fs acult to maintadr an accurate Aaittana sako wih Lmperatyre vasdatons w Explib the warkity of R2R ladda DAC 1 neat | dytwit diagram? th At : vhs aes ’ Ada dd, 4 38 Re Aska t tRokt > THE type of dhe wes only a& wosistos Rand ak tena fk fe cow tr fabsiGte all AsiSes on the Chip: > Vue) valu of deft Aang tem %5k2 to doka. > The nesisers [R-2R] ave bo arvanged as fo brma ladde netsaxk 05 shown above. > Le the digttal Tp to be 3 bit bfrawy The Switch posfHors ave Shown dotled fh above fouve. > The Creuit fs me dyawn ou Shown below -; ~V Rep, > fied voltae ot node s [vel hh QrioR=R fis 2RxBR wer el 2 DRDR | tly R4R= 2R my ORI] 2R =R fn RR=2R- Te eqpivalent xestance 10 the lett . The modified ckt fs shaven belotd: ¥ Because Vivtual ground al a)p termfrals of, op Pimp b the pokntial af fnierting Ferettnal fs eho vols g node 8 =2k. The me yal f¢ modified as below s Ie 2ENB = sy = 2 z ss Vy if = turrent (2)= Ve. . - 8a. L\ ay QRL2R eR aes 3 ay a Jae ie DR = (May = DAE eek a > Voltage at node § ~ The oxtiginal Civout may be drawn again at hilo\ Perri < | a: iy we have Cleled loop gain of fnvesting amplifies fs Np gee eo Vis GRR R Hoe v= We 4 2 eee Ne ET ed a By Same analyas, the e & v-ol0 8 St and the Ve & b= bol fs SE - | ay, ay Draw the Schematic block diag yam of duct $lope AOC and analyze the digits! oufput exprewion. . Bt Dual dope Adc 6 alto known of Infegyvoled typ 46. £ %; the analog yp Voltage, ae volloge bait aye : iovorted Into fanctoral % Hime 10 %y Imeors integrals ard then mead ured by means of Counts ie Le agi =~ Hip Flops |~—aas[ QPERBTION + a 7 > CASE-4* [hen $-4; Pe: Suthh fs. connected fo technica) : | Terminal 4 thot fs y at to: > The analog Tp Voltage ih Vy gets applied at the fnves ting terial of finteg vole > The tnleg vets olp voltage V, ts applied fo Ve terminal g, the Compasads with the terminal Connected to the qnound - el oi Moy = aq J “de eo) <. The Compasates olp goo bfgh, tt enables AND gate are fhe dees pule seacher the Counks end counrtes beg fins Counting the Clock pultes. ' > OSE -2? hlhen bo > M the end of 9? clock paler, the ov Hous HSE EFF op the lounte goer high This Gsa the Swith %* to Gof kh Kom position 1 te posftin2 be. Switch %¢? fs Connected to — Veep + 7 Ninh Gs pied ae > Integralseee leita eS fe |. The Fokeqvotes op voltage Vos fs applied to -Ve Kavnfial of | Comparahs , with tre fermfnal atgsound: AS a Sesull comparadet ofp goa low, ft disable Aw gate | and the binary dounts ges Aeset, he Countes dfops Counting Clock pulses. ee chasge Volk ¢ = Df chasge Vo tage =v eae ett te WEL, boar Bef 3S as na Bid then | t, K Ue a by Llsdfe the aclvantages and PiSodvantages of Duct! ~Clope Adc) As She aclvantaget oh Dual Slope Abe ate: —> Tt has high acturacy > Tis Comparably cheaper. > TF provide gyeates notte Hin und ty > T hat low Conversion time. -> The Count ‘an be desfgned to be fn bfmwty, BoD & any tes desided dicplay evnE “athe disadvantages of dual Slope APC ate : a The Speed of Opevatien fs low - | ? LT i the sowet amsng all oftes Ades. are has com plated Aycuit- 7D fs higher fin cost- 8y klbfch % the parallel Compasals Ape? Explafo the operation and distum the met and ce mei? [AS > The Postale! Comparator foc f alwo Known ak Flash Type moc. 2fra ft cloet the lonveysion Very vapidly. > The foe fs Calle) pasxalle) compuas Abe, beCue al) the (ern patath ined fp the drat ave paralbl. > Advan tages > ClProplest of all ofhes Convesters. > High peed = Di&advan tage> —> Mott erpentive > Le aluyedl. Bz g- Bit ADC Aequises 4 Com/pascdass, 8-bit Adc Aequises & Com divides > The dvadt conkish of Aevistyye Gibderirctwask 2 ro. ¢ ©p- a Comportals and & b 3 Prdostty endacley. > The inverting tesmfnals of al! the OP-amps eve Connected to he analog r]p Vip and the faverting L/p umirelye ee, ©. : | fr eg bala levels of yep. Vollage (Yee) prodtsced > The fe we ae es | | $fnal Me olfage (Vea)is equal to full Scale IP > AU the safictos ave G equal magnitude | (> The voltige levels at the neds ave equally divided b)ue the Rep. voltage (Upc) and the ground. > The main putpae of build fing the Gyust fh thic fashion 5 to Compare the Fp Analog Vollege (Vy) with bitch eh the nede vohages. |, The basfe ckt dgm of 32-bit Hash type Apc fs j Vtn( thaloy Zp)— lompatahs gives o/P q Alo de percling on whether the ' P Signal level Bs great than & len Haan Yeperente Voltage | ee ee ve ar ae > Tout tate of APSE Tp volagelVr) |X Xe Xe X4 Xs % %o| Ya 4, Yo 0.0) 0 OO OO Olay Y oby%k |0000090%9!|0 00 yout? Fe%e|0. © O09 Ge | o | Yok 3¢¥e1On0 OPO. aa! eo 3gMe to HpveiOO OO 1 \' ua Abe to-Shye | © ©, Otel tel 20 dpyete gO ON | he ie |O | Gee ee ee ta ie©) Ay Explafo about Counter type Apc wth avaut diagram and the opelatten? The Basic paindple employed fn This ype of Abe bs that tinea Ramp Can be produced by Counting the Olp a Counter to the tpg bac: fa | fx sie vigil Buthes hee ty de Vin >Yege —b 4 Lele of Comparator] jiy dL Mbp > Min => 0 [ No clock pulbe] —> Bapjo f wed to. lakeh the digftel dada @ ofp cides. ~> counter £5 Frftfally 07 then Doe fntialse ‘0? Hren When we Comake then the output wil! be legfe 4 and ft hos gen to AND gate « > Conke| Gycbt Bote 0s clear Gad and dota to Count agaln — Dibadvantages: Convers fon tine % not tixed and f depend on the amplitude of the ‘FIP Voltage ard i amplitude fheyeasing then It fakes toro time|? Madimum conversfon time vA be thee fp Ves[ Fill Kal | Voltage] ; E cman) = (2) Tae > No-q bets Tye> Clock ¢igna) hequency > Counter will Skett fom %o? = Cenvevm lfne fs citjesent #8 diferent TIP Sample iM Ft fs dive Hy pyopasticnal te the TIP Sigtel. No es lol enh —> DFpflad dada FS Labching vofth bupter. 2a) acs ig tao a tnale4ie ee eae 5| Draws the Ghematic diagram «sty DIA Conuetter. Use - Vesisrante, Values whose vrokos ave murniples =f 2 ach Bx Plan the operation el Converters astthy outpt Expression, Digital 40 Analog converter AC) 1— (sa) | Phas ot | ean | net ; DAC ees : Vo (Analog °[?) | Puest de ys (Ls) Sheseatie fy OI maui: Saleriipesyae aC 3S Oe Lie Gnasy Laer (0), edhose argits oe dis dry aviv ee ee Odes Ag ett dy DS FLEIs combined with Re Lesence vottaye Wa) & the ccesuting olp oA? aniales Sign The amalog ole Vehase is Cepressed 5, eteveel Aum os gt a clntd WHECE, ED Seoting Cactr Hida W Lsusty unite. Ness Fan Scate Voltye Ar) Mae bet wergtd Wes 2 AyD USe bit wh eight “Ves >)008 ue De didrds 100 R= 25N-L0kKA (-vR) DWH tyee el DAC User Only 2 Feretos” RE2eA, whente if \s easy te fabricate “all Wesistors OF The chip =) Cferoly Valued Hy Yesistoss Yarge pee eric fo) DOE NE SD The verses (Q-2e) axe So -ananged of te farina a ladder Nlw as Clow above dvaaraly = bee Wee eee Neale SN eee Saskdy Pose 5: ose grown dotted in As que The Saye is Nedvous Nj; 1 mn 38 chown belo beret V3, eect males Le Ess ie S ee “To. Neate eens hace, Wie) a, ance VW) 2eynr2ese ae aod = AX.) ass UB) Re@ 2h fo) aniio2e = Key uate Jo The eqpiuated sesierancs to tte left of Mode 2228 aan osacagmmeine is cscsShon belod. # Beraure ay Virtual qrosunel at “(ep terminals of) op- ANE 2e dhe Poten Hal ad \ntenting fexeninad “18 Bere Ato lis . < ae i A Shown Lele The ovoxe eet madified o4 Sho eer HA 2@ = 3 fo Wea - ra ama NT apt 2 4 Ne i das a canes (= =e 2 3M a ao 2% Te ® z => \wttege ot oote@) yge Pere _ -20Vp 20 _-Ve z ean ga 3 SD The orignal cet may be redrawn as Lenor, a @ 2e A 7 No ae 4 We have Closed loop “Gedy ) Tmvering wel reg sae Uae | is, Ree & & RENCE =Ve q tok beta ints ee feng yo= 2 [eX Vo = 2 wots head By Same Analysis jthe ©fe Nertage Ssean=cBa0 drda;, the ofp Neta4< Se psbo hs6. Explain the Operation ely Succesive Dpprreieredtion ADC with | mead Cixculd Dissvatn-t Succeswe Approvimahon “Type AOC > Conve sion hme Va Con nhes AOC rs depencting “ON \Ip_ Aroleg awaleg No Wage . dupe Smad The Fravkng tate Notlaye ord ‘Rede oy ‘le ane and its convesion HME doesw't 3 SAC Yedutes | degends “on Yo anaes Yotaye. Nin J & nope ee Successive eat | A pporimation Reqicter fae tt ( vig ate) dat ole DDL wetke Aval {| exvor process & Hos portculay Lode GATE U Cones «Newest S the ne4- ADC ‘Olp The Chet USES 0 Succesve ApPreKimection Reqpries (S48) DAC and a comparcdor: Operation! “the lage Mea af using SA8 hate Grd by thet cid EXKOK HOCELS, > Dwebay SAR sets the MGB “bet Lee) and all the other tris axe Set aus Ta: Soon of The Stavt gignal Oe , to So! Pl the Converter is G-Bit Legaverter the wnittel setting wWoeard bbe 1000.The Sp Nig te At DAC er this sHiak) Cate is epee oss analog \[p Nye Caseli) TL WrdVg i.e, he analog Hp Mi is grete than BAC ofp (Wa) V4 Waptics hed the Sant tae Goo ss) tae the Coweet Ayital se presenlalson oy (ny. Fa Aas Cake, the M3e Bt (di) tele ak 1, the next Use wot AG the proces Xe pected We) tivo Case (ii) TE WS UZ rk rplies thed the the) code loos gneder than the tewect dignal — Vepre seectedion e(lui). Rn Hac Gie phe MES “Gk Set tp DB ard Me next Loe bit Set toh. and the process xepeoted ve, Dioo J ConverSgion Time VT. =Hent) eC Periedtounter Hype AOC wR Kesh Grout diagram 7 a] Explain the Mention its dae bork s? Counter ype ADL — | 1S thed ayed andtis type noe The Raye prirtipte empl the O[p ols Nineay Ramp Can ve produced by | Counter tothe ifp ef Dac. [i conde HH Control tag ic. | Aka oe (iy Countey la? Clea r—— t t Baller a { feat: aise gl? BAC UW) BE Atin>® Mone SL Cofp ef Comparator) WW) BL Vone 7uin DS OLN Ctoce Pulse) > Buller WW wed fo latch the dig) data @ olp Stes ~ Counter Ag wally ‘Oo then DAC Imifating “Oo! then When woe Compare them the output wotil be logic ef. and iL has given to AND qede, contol! tcudt acts of Bleak CWO and daa to Count aoain, Disadvantages: ConweNsion “me is — OW the amplitade ol the \P VS weve aSing hen Th takes Mie AME, not fixed and te depends ‘loHage and if ampitucte = Max. conversion ime wit be there: in Ves {Lan scatte VO linge)N-po.a bits Tey — Clock signal Le equency: ae =) canter With Start from ‘0! atfevedt ov diffe “le Gamole. ans} SD Convasion time IS Ne ig. divectty pro por Rona ‘to the 4[P signal a . N ey frog Ve 5 — Noa Time SD Vigtal data Is latchins with butler. ded to OAc; Pere the forowing terms aA Yeu Linearity and ‘Restution. Lineaxity exvos? TE wnny be dekned -ah the diferente bles the actual ojp ond Mdeal lp yaeo) OlP AES Acived olp: 1pResoiution (QR) = The Ramber ey AiELever| ‘Analogy Op Values thal the DAC can provide &) PE WG the Smallesd charge in the Analog “O(p Carreal by Change Aiqret a t[p- ee |e Fall cate Ofp Voltage ¥ 100 Fan Scale ofp vettese © |Nops ps K Step Sire [ie es a No.of Steps Noes = Faw Sate ofp Voriase.