VIPer53EDIP - E

VIPer53ESP - E

OFF-line Primary Switch

Features
■ Switching frequency up to 300kHz
■ Current mode control with adjustable limitation
■ Soft start and shut-down control
■ Automatic burst mode in standby condition
(“Blue Angel“ compliant ) PowerSO-10 DIP-8
■ Undervoltage lockout with Hysteresis
Typical applications cover offline power supplies
■ Integrated start-up current source
with a secondary power capability ranging up to
■ Over-temperature protection 30W in wide range input voltage, or 50W in single
■ Overload and short-circuit control European voltage range and DIP-8 package and
40W in wide range input voltage, or 65W in single
■ Overvoltage protection
European voltage range and PowerSO-10
■ In compliance with the 2002/95/EC European package, with the following benefits:
Directive – Overload and short-circuit events
controlled by feedback monitoring and
Description delayed device reset;
– Efficient standby mode by enhanced pulse
The VIPer53E combines an enhanced current skipping.
mode PWM controller with a high voltage
– Integrated start-up current source is
MDMesh Power MOSFET in the same package.
disabled during normal operation to reduce
Block diagram the input power.
OSC DRAIN

ON/OFF

OSCILLATOR

PWM
LATCH
OVERTEMP. S BLANKING TIME
R1
DETECTOR SELECTION
FF Q 1V
R2
R3 R4 R5

PWM
UVLO COMPARATOR 0.5V HCOMP
COMPARATOR
150/400ns
VDD
BLANKING CURRENT
8.4/ AMPLIFIER
11.5V
STANDBY
8V COMPARATOR Vcc
0.5V

125k IC OMP
4V
OVERLOAD
COMPARATOR
4.4V

OVERVOLTAGE
COMPARATOR
4.5V

18V

TOVL COMP SOURCE

January 2006 DocRev1 1/31

www.st.com 31
Contents VIPer53EDIP - E / VIPer53ESP - E

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Rectangular U-I Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Secondary Feedback Configuration Example . . . . . . . . . . . . . . . . . . . . 9

6 Current Mode Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8 High Voltage Start-up Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . 13

9 Short-Circuit and Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . 15

10 Regulation Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Special Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

12 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

13 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

15 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Electrical data

1 Electrical data

1.1 Maximum rating

Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 1. Absolute maximum rating

Symbol Parameter Value Unit

VDS Continuous Drain Source Voltage (TJ= 25 ... 125°C) (1) -0.3 ... 620 V

ID Continuous Drain Current Internally limited A

VDD Supply Voltage 0 ... 19 V

VOSC OSC Input Voltage Range 0 ... V DD V

ICOMP
COMP and TOVL Input Current Range (1) -2 ... 2 mA
ITOVL

Electrostatic Discharge:
VESD Machine Model (R = 0Ω; C = 200pF) 200 V
Charged Device Model 1.5 kV
TJ Junction Operating Temperature Internally limited °C
TC Case Operating Temperature -40 to 150 °C

TSTG Storage Temperature -55 to 150 °C

1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ
should be inserted in series with the TOVL pin.\

1.2 Thermal data

Table 2. Thermal data

Symbol Parameter PowerSO-10 (1) DIP-8 (2) Unit

RthJC Thermal Resistance Junction-case Max 2 20 °C/W

RthJA Thermal Resistance Ambient-case Max 60 80 °C/W
1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the DRAIN pin.
2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the device tab.

DocRev1 3/31
Electrical characteristics VIPer53EDIP - E / VIPer53ESP - E

2 Electrical characteristics

TJ = 25°C, VDD = 13V, unless otherwise specified

Table 3. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

Drain-Source
BVDSS ID = 1mA; VCOMP = 0V 620 V
Voltage
Off State Drain
IDSS VDS = 500V; VCOMP = 0V; Tj = 125°C 150 µA
Current
ID = 1A; VCOMP = 4.5V; VTOVL = 0V
Static Drain-Source
RDS(on) TJ = 25°C 0.9 1 Ω
On State Resistance
TJ = 100°C 1.7 Ω

tfv Fall Time ID = 0.2A; VIN = 300V (1) 100 ns

trv Rise Time ID = 1A; VIN = 300V (1) 50 ns

Coss Drain Capacitance VDS = 25V 170 pF

Effective Output
CEon 200V < V DSon < 400V (2) 60 pF
Capacitance
1. On clamped inductive load
2. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain
to source voltage VDSon and the following formula:

1 2 V DSon 1.5
E ton = --- ⋅ C Eon ⋅ 300 ⋅ ⎛⎝ ----------------⎞⎠
2 300

Table 4. Oscillator Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Oscillator Frequency RT = 8kΩ; CT = 2.2nF

FOSC1 95 100 105 kHz
Initial Accuracy Figure 15 on page 23
RT = 8kΩ; CT = 2.2nF
Oscillator Frequency Figure 17 on page 24
FOSC2 93 100 107 kHz
Total Variation VDD = V DDon ... VDDovp;
TJ = 0 ... 100°C

Oscillator Peak
VOSChi 9 V
Voltage
Oscillator Valley
VOSClo 4 V
Voltage

4/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Electrical characteristics

Table 5. Supply Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Drain Voltage Starting

VDSstart VDD = 5V; IDD = 0mA 34 50 V
Threshold
VDD = 0 ... 5V; VDS = 100V
IDDch1 Startup Charging Current -12 mA
Figure 9 on page 22
IDDch2 Startup Charging Current VDD = 10V; VDS = 100VFigure 9. -2 mA

Startup Charging Current VDD = 5V; V DS = 100VFigure 11.

IDDchoff 0 mA
in Thermal Shutdown TJ > TSD - THYST

Operating Supply Current

IDD0 Fsw = 0kHz; V COMP = 0V 8 11 mA
Not Switching
Operating Supply Current
IDD1 Fsw=100kHz 9 mA
Switching
VDD Undervoltage
VDDoff Figure 9 on page 22 7.5 8.4 9.3 V
Shutdown Threshold
VDDon VDD Startup Threshold Figure 9. 10.2 11.5 12.8 V
VDD Threshold
VDDhyst Figure 9. 2.6 3.1 V
Hysteresis
VDD Overvoltage
VDDovp Figure 9. 17 18 19 V
Shutdown Threshold

Table 6. Pwm Comparator Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCOMP = 1 ... 4 V Figure 14.

HCOMP ∆VCOMP / ∆IDPEAK
dID/dt = 0 1.7 2 2.3 V/A
VCOMPos VCOMP Offset dID/dt = 0 Figure 14. 0.5 V
ICOMP = 0mA; VTOVL = 0V
Peak Drain Current
IDlim Figure 14.
Limitation 1.7 2 2.3 A
dID/dt = 0

Drain Current VCOMP = VCOMPovl ; VTOVL = 0V

IDmax
Capability dID/dt = 0 1.6 1.9 2.3 A
Current Sense Delay
td ID = 1A 250 ns
to Turn-Off
VCOMP Blanking Time
VCOMPbl Figure 10 on page 22 1 V
Change Threshold
tb1 Blanking Time VCOMP < VCOMPBLFigure 10. 300 400 500 ns

tb2 Blanking Time VCOMP > VCOMPBLFigure 10. 100 150 200 ns
tONmin1 Minimum On Time VCOMP < VCOMPBL 450 600 750 ns

DocRev1 5/31
Electrical characteristics VIPer53EDIP - E / VIPer53ESP - E

Table 6. Pwm Comparator Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

tONmin2 Minimum On Time VCOMP > VCOMPBL 250 350 450 ns

VCOMP Shutdown
VCOMPoff Figure 13 on page 23 0.5 V
Threshold
VCOMPhi VCOMP High Level ICOMP=0mA (1) 4.5 V
ICOMP COMP Pull Up Current VCOMP= 2.5V 0.6 mA

1. In order to ensure a correct stability of the internal current source, a 10nF capacitor (minimum value 8nF)
should always be present on the COMP pin.

Table 7. Overload Protection Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCOMP Overload ITOVL = 0mA Figure 7 on page 20

VCOMPovl 4.35 V
Threshold (1)

VDD = VDDoff ... VDDreg;

VCOMPhi to VCOMPovl ITOVL= 0mA
VDIFFovl 50 150 250 mV
Voltage Difference
Figure 7. (1)

VTOVL Overload
VOVLth Figure 7. 4 V
Threshold
tOVL Overload Delay COVL = 100nF Figure 7. 8 ms
1. VCOMPovl is always lower than VCOMPhi

Table 8. Over temperature Protection Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit
Thermal Shutdown
TSD Figure 11 on page 22 140 160 °C
Temperature
Thermal Shutdown
THYST Figure 11 on page 22 40 °C
Hysteresis

Table 9. Typical Output Power Capability

European US / Wide range
Type
(195 - 265Vac) (85 - 265Vac)
VIPer53EDIP-E 50W 30W
VIPer53ESP-E 65W 40W

6/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Pin connections and function

3 Pin connections and function

Figure 1. Pin connection (top view)

COMP 1 8 TOVL DRAIN

NC 1 10 SOURCE
OSC 2 7 VDD NC 2 9 NC
NC 3 8 NC
SOURCE 3 6 NC VDD 4 7 OSC
TOVL 5 6 COMP
SOURCE 4 5 DRAIN

DIP-8 PowerSO-10

Figure 2. Current and voltage conventions

IDD ID

VDD DRAIN

IOSC
OSC
15V

VDS
VDD TOVL COMP SOURCE

ITOVL
VOSC

ICOMP
VTOVL

VCOMP

Table 10. Pin function

Pin Name Pin Function

Power supply of the control circuits. Also provides the charging current of the external
capacitor during start-up.
The functions of this pin are managed by four threshold voltages:
VDD
- VDDon: Voltage value at which the device starts switching (Typically 11.5 V).
- VDDoff: Voltage value at which the device stops switching (Typically 8.4 V).
- VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V).
SOURCE Power MOSFET source and circuit ground reference.
Power MOSFET drain. Also used by the internal high voltage current source during
DRAIN
the start-up phase, to charge the external VDD capacitor.

Allows the setting of the dynamic characteristic of the converter through an external
passive network. The useful voltage range extends from 0.5V to 4.5V. The Power
COMP MOSFET is always off below 0.5V, and the overload protection is triggered if the
voltage exceeds 4.35V. This action is delayed by the timing capacitor connected to the
TOVL pin.
Allows the connection of an external capacitor for delaying the overload protection,
TOVL
which is triggered by a voltage on the COMP pin higher than 4.4V.
OSC Allows the setting of the switching frequency through an external Rt-Ct network.

DocRev1 7/31
Rectangular U-I Output characteristics VIPer53EDIP - E / VIPer53ESP - E

4 Rectangular U-I Output characteristics

Figure 3. Off Line Power Supply With Optocoupler Feedback

F1

C1
AC IN D1

T1
R2
R1 C2
C3

T2

D2

L1
D4
D3 C8 C9 DC OUT
R4

R3
VDD DRAIN
C10

OSC
CONTROL

R8

COMP TOVL SOURCE

C4
U2

R9
R5
C12 1k
C5
10nF

C11
C7 C6
R7

U3

R6

8/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Secondary Feedback Configuration Example

5 Secondary Feedback Configuration Example

The secondary feedback is implemented through an optocoupler driven by a programmable

zener diode (TL431 type) as shown in Figure 3 on page 8
The optocoupler is connected in parallel with the compensation network on the COMP pin
which delivers a constant biasing current of 0.6mA to the optotransistor. This current does
not depend on the compensation voltage, and so it does not depend on the output load
either. Consequently, the gain of the optocoupler ensures a constant biasing of the TL431
device (U3), which is responsible for secondary regulation. If the optocoupler gain is
sufficiently low, no additional components are required to a minimum current biasing of U3.
Additionally, the low biasing current protects the optocoupler from premature failure.
The constant current biasing can be used to simplify the secondary circuit: instead of a
TL431, a simple zener and resistance network in series with the optocoupler diode can
insure a good secondary regulation. Current flowing in this branch remains constant just as
it does by using a TL431, so typical load regulation of 1% can be achieved from zero to full
output current with this simple configuration.
Since the dynamic characteristics of the converter are set on the secondary side through
components associated to U3, the compensation network has only a role of gain
stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed
value of 2.2kΩ, offering the possibility of using C7 as a soft start capacitor: When starting up
the converter, the VIPer53E device delivers a constant current of 0.6mA on the COMP pin,
creating a constant voltage of 1.3V in R5 and a rising slope across C7. This voltage shape,
together with the operating range of 0.5V to 4.5V provides a soft startup of the converter.
The rising speed of the output voltage can be set through the value of C7. The C4 and C6
values must be adjusted accordingly in order to ensure a correct startup.

DocRev1 9/31
Current Mode Topology VIPer53EDIP - E / VIPer53ESP - E

6 Current Mode Topology

The VIPer53E implements the conventional current mode control method for regulating the
output voltage. This kind of feedback includes two nested regulation loops:
The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET
output transistor is on, the inductor current (primary side of the transformer) is monitored
with a SenseFET technique and converted into a voltage. When VS reaches VCOMP, the
power switch is turned off. This structure is completely integrated as shown on the Block
Diagram of Figure on page 1, with the current amplifier, the PWM comparator, the blanking
time function and the PWM latch. The following formula gives the peak current in the Power
MOSFET according to the compensation voltage:
V COMP – V COMPos
I Dpeak = --------------------------------------------------
H COMP

The outer loop defines the level at which the inner loop regulates peak current in the power
switch. For this purpose, VCOMP is driven by the feedback network (TL431 through an
optocoupler in secondary feedback configuration, see Figure 3 on page 8) and is sets
accordingly the peak drain current for each switching cycle.
As the inner loop regulates the peak primary current in the primary side of the transformer,
all input voltage changes are compensated for before impacting the output voltage. This
results in an improved line regulation, instantaneous correction to line changes, and better
stability for the voltage regulation loop.
Current mode topology also provides a good converter start-up control. The compensation
voltage can be controlled to increase slowly during the start-up phase, so the peak primary
current will follow this soft voltage slope to provide a smooth output voltage rise, without any
overshoot. The simpler voltage mode structure which only controls the duty cycle, leads
generally to high current at start-up with the risk of transformer saturation.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in the case of current spikes caused by primary side
transformer capacitance or secondary side rectifier reverse recovery time when working in
continuous mode.

10/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Standby Mode

7 Standby Mode

The device offers a special feature to address the low load condition. The corresponding
function described hereafter consists of reducing the switching frequency by going into burst
mode, with the following benefits:
– It reduces the switching losses, thus providing low consumption on the mains lines.
The device is compliant with “Blue Angel” and other similar standards, requiring less
than 0.5 W of input power when in standby.
– It allows the regulation of the output voltage, even if the load corresponds to a duty
cycle that the device is not able to generate because of the internal blanking time,
and associated minimum turn on.
For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM
latch and the Power MOSFET in the Off state as long as VCOMP remains below 0.5V (See
Block Diagram on page 2). If the output load requires a duty cycle below the one defined by
the minimum turn on of the device, the VCOMP net decreases its voltage until it reaches this
0.5V threshold (VCOMPoff). The Power MOSFET can be completely Off for some cycles, and
resumes normal operation as soon as VCOMP is higher than 0.5V. The output voltage is
regulated in burst mode. The corresponding ripple is not higher than the nominal one at full
load.
In addition, the minimum turn on time which defines the frontier between normal operation
and burst mode changes according to VCOMP value. Below 1.0V (VCOMPbl), the blanking
time increases to 400ns, whereas for higher voltages, it is 150ns Figure 10 on page 22 The
minimum turn on times resulting from these values are respectively 600 ns and 350 ns,
when taking into account internal propagation time. This brutal change induces an
hysteresis between normal operation and burst mode as shown on Figure 10 on page 22
When the output power decreases, the system reaches point 2 where VCOMP equals
VCOMPbl. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding
the effective turn-on time that should be needed at this output power level. Therefore the
regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst
mode and to control the output voltage. The corresponding hysteresis can be seen on the
switching frequency which passes from FSWnom which is the normal switching frequency set
by the components connected to the OSC pin and to FSWstby. Note: This frequency is
actually an equivalent number of switching pulses per second, rather than a fixed switching
frequency since the device is working in burst mode.
As long as the power remains below PRST the output of the regulation loop remains stuck at
VCOMPsd and the converter works in burst mode. Its “density” increases (i.e. the number of
missing cycles decreases) as the power approaches P RST and finally resumes normal
operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be
seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power
level.
The power points value PRST and PSTBY are defined by the following formulas:
1 2 2 1
P R ST = --- • F SWnom • ( tb 1 + td ) • V IN • -------
2 Lp

1 2
P STBY = --- • F SWnom • Ip ( V COMPbl ) • Lp
2

DocRev1 11/31
Standby Mode VIPer53EDIP - E / VIPer53ESP - E

Where Ip(VCOMPbl2) is the peak Power MOSFET current corresponding to a compensation

voltage of VCOMPbl (1V). Note: The power point PSTBY where the converter is going into
burst mode does not depend on the input voltage.
The standby frequency FSWstby is given by:
P STBY
P SWstby = ----------------- • F SWnom
P RST

The ratio between the nominal and standby switching frequencies can be as high as 4,
depending on the Lp value and input voltage.

Figure 4. .Standby Mode Implementation

ton
3
600ns 1
Minimum
turn on 2
350ns

VCOMP
VCOMPsd VCOMPbl
VCOMPoff

PIN

PRST 1

PSTBY 2
FSW
FSWstby FSWnom

12/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E High Voltage Start-up Current Source

8 High Voltage Start-up Current Source

An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits in standby
mode with reduced consumption, and also supplies the external capacitor connected to the
VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the
UVLO logic, the device turns into active mode and starts switching. The start-up current
generator is switched off, and the converter should normally provide the needed current on
the VDD pin through the auxiliary winding of the transformer, as shown on Figure 3 on
page 8.
The external capacitor CVDD on the VDD pin must be sized according to the time needed by
the converter to start-up, when the device starts switching. This time tss depends on many
parameters, including transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin and possible secondary feedback
circuit. The following formula can be used for defining the minimum capacitor needed:
I D D1 ⋅ tss
C VD D > ------------------------
V DDhyst

Figure 9 on page 22 shows a typical start-up event. V DD starts from 0V with a charging
current IDDch1 at about 9 mA. When about VDDoff is reached, the charging current is reduced
down to IDDch2 which is about 0.6mA. This lower current leads to a slope change on the VDD
rise. Device starts switching for VDD equal to VDDon, and the auxiliary winding delivers some
energy to VDD capacitor after the start-up time tss.
The charging current change at VDDoff allows a fast complete start-up time tSDU, and
maintains a low restart duty cycle. This is especially useful for short circuits and overloads
conditions, as described in the following section.

DocRev1 13/31
High Voltage Start-up Current Source VIPer53EDIP - E / VIPer53ESP - E

Figure 5. Start-up Waveforms

IDD

IDD1

t
IDDch2

IDDch1

VDD tSS

VDDreg
VDDst
VDDsd
tSU

14/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Short-Circuit and Overload Protection

9 Short-Circuit and Overload Protection

A VCOMPovl threshold of about 4.4V has been implemented on the COMP pin. When VCOMP
goes above this level, the capacitor connected on the TOVL pin begins to charge. When
reaching typically VOVLth (4V), the internal MOSFET driver is disabled and the device stops
switching. This state is latched because of to the regulation loop which maintains the COMP
pin voltage above the V COMPovl threshold. Since the VDD pin does not receive any more
energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the
device is reset, recharging the VDD capacitor for a new restart cycle. Note: If VCOMP drops
below the VCOMPovl threshold for any reason during the VDD drop, the device resumes
switching immediately.
The device enters an endless restart sequence if the overload or short circuit condition is
maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries
to restart, thus delivering its full power capability to the output. In order to keep the whole
converter in a safe state during this event, DRST must be kept as low as possible, without
compromising the real start-up of the converter. A typical value of about 10% is generally
sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the
following conditions:
–6
C OVL > 12.5 ⋅ 10 ⋅ tss

4 1 C OVL ⋅ I D Dch2
C VDD > 8 ⋅ 10 ⋅ ⎛ -------------- – 1⎞ ⋅ ------------------------------------
⎝D ⎠ V DDhyst
RST

Refer to the previous start-up section for the definition of tss, and CVDD must also be
checked against the limit given in this section. The maximum value of the two calculus will
be adopted.
All this behavior can be observed on Figure 2 on page 7. In Figure 7 on page 20 the value of
the drain current Id for VCOMP = VCOMPovl is shown. The corresponding parameter IDmax is
the drain current to take into account for design purposes. Since IDmax represents the
maximum value for which the overload protection is not triggered, it defines the power
capability of the power supply.

DocRev1 15/31
Regulation Loop Stability VIPer53EDIP - E / VIPer53ESP - E

10 Regulation Loop Stability

The complete converter open loop transfer function can be built from both power cell and
the feedback network transfer functions. A theoretical example can be seen in Figure 11 on
page 22 for a discontinuous mode flyback loaded by a simple resistor.
A typical schematic corresponding to this situation can be seen on Figure 3 on page 8. The
transfer function of the power cell is represented as G(s) in .Figure 11 on page 22 It exhibits
a pole which depends on the output load and on the output capacitor value. As the load of a
converter may change, two curves are shown for two different values of output resistance
value, RL1 and R L2. A zero at higher frequency values then appears, due to the output
capacitor ESR. Note: The overall transfer function does not depend on the input voltage
because of the current mode control. A typical regulation loop is shown on Figure 3 on
page 8 and has a fixed behavior represented by F(s) on Figure 11 on page 22. A double
zero due to the R 1-C1 network on the COMP pin and to the integrator built around the TL431
and R2-C2 is set at the same value as the maximum load RL2 pole.
The total transfer function is shown as F(s). G(s) at the bottom of Figure 11 on page 22. For
maximum load (plain line), the load pole begins exactly where the zeros of the COMP pin
and the TL431 stop, and this results in a first order decreasing slope until it reaches the zero
of the output capacitor ESR. The point where the complete transfer function has a unity gain
is known as the regulation bandwidth and has a double interest:
– The higher it is, the faster the reaction will be to an eventual load change, and the
smaller the output voltage change will be.
– The phase shift in the complete system at this point has to be less than 135° to
ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a
second-order gives 180°.
In Figure 3 on page 8, the unity gain is reached in a first order slope, so the stability is
ensured.
The dynamic load regulation is improved by increasing the regulation bandwidth, but some
limitations have to be respected:
1. As the transfer function above zero due the ESR capacitor is not reliable (the ESR itself
is not well specified, and other parasitic effects may take place), the bandwidth should
always be lower than the minimum of FC and ESR zero
2. As the highest bandwidth is obtained with the highest output power (plain line with RL2
load in Figure 3, the above criteria will be checked for this condition and allows the
value of R4 if R1 is set to a fixed value (e.g., (2.2kΩ).
As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load
in Figure 3), the above criteria will be checked for this condition and allows to define the
value of R 4, if R1 is set fixed (2.2kΩ, for instance). The following formula can be derived:
P G ⋅R
MAX O 1
R = --------------------- ⋅ --------------------------------------------------------
4 P F ⋅R ⋅C
O UT2 BW2 L2 OUT

2
V
OUT
with: P
O UT2
= -----------------
R L2

1 2
and: P
MAX
= --- ⋅ L ⋅ I
2 P LIM SW
⋅F

Go is the current transfer ratio of the optocoupler.

16/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Regulation Loop Stability

The lowest load gives another condition for stability: The frequency FBW1 must not
encounter the third order slope generated by the load pole, the R1-C1 network on the
COMP pin and the R2-C2 network at the level of the TL431 on secondary side. This
condition can be met by adjusting both C1 and C2 values:
R ⋅C P
L1 OUT OU T1
C > ----------------------------------- ⋅ ---------------------
1 GO PMAX
2
6.3 ⋅ --------- ⋅ R 1
R4

R L1 ⋅ C OUT P OU T1
C > ----------------------------------------------- ⋅ ---------------------
2 G P
O MAX
6.3 ⋅ --------- ⋅ R ⋅ R
R 1 2
4

2
V OUT
with: P OUT1 = -------------------
R
L1

The above formula gives a minimum value for C1. It can be then increased to provide a
natural soft start function as this capacitor is charged by the current ICOMP at start-up.

DocRev1 17/31
Special Recommendations VIPer53EDIP - E / VIPer53ESP - E

11 Special Recommendations

10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to
ensure correct stability of the internal current source Figure 12 on page 22.
In order to improve the ruggedness of the device versus eventual drain overvoltages, a
resistance of 1kΩ should be inserted in series with the TOVL pin, as shown on Figure 12 on
page 22
Note: This resistance does not impact the overload delay, as its value is negligible prior to the
internal pull-up resistance (about 125kΩ).

18/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Software Implementation

12 Software Implementation

All the above considerations and some others are included included in ST design software
which provides all of the needed components around the VIPer device for specified output
configurations, and is available on www.st.com.

DocRev1 19/31
Operation pictures VIPer53EDIP - E / VIPer53ESP - E

13 Operation pictures

Figure 6. Rise and Fall time

ID

C<<C OSS

C L D

t
VDD DRAIN
VDS
300V
OSC
CONTROL
90%

tfv trv
COMP TOVL SOURCE

10% t

Figure 7. Overloaded Event

VDD
Normal Abnormal
operation operation

VDDon
VDDoff

VCOMP VDIFFovl

VTOVL

VOVLth
tOVL

VDS
Not
switching

Switching

20/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Operation pictures

Figure 8. Complete Converter Transfer Function

1
------------------------------------------
π⋅R ⋅C
L1 OUT
P
M AX
3.2 ⋅ ---------------------
P
OU T1 1
------------------------------------------
π ⋅R ⋅C
P L2 O UT
MA X
3.2 ⋅ ---------------------
P O UT2

1
---------------------------------------------------
2 ⋅ π ⋅ ESR ⋅ C
OUT

FS

1
--------------------------------------------------------------------
2⋅π⋅R ⋅C
COM P COM P
FC
R
1
G ⋅ -------
O R
4

1
F S. GS

F BW2
1
FBW1

DocRev1 21/31
Operation pictures VIPer53EDIP - E / VIPer53ESP - E

Figure 9. Start-up VDD current Figure 10. Blanking Time

tb
IDD
tb1
IDD0
VDDhyst

VDDoff VDDon
VDD

IDDch2
tb2
VDS = 100 V
FSW = 0 kHz VCOMP
IDDch1 VCOMPbl VCOMPhi

Figure 11. Thermal Shutdown Figure 12. Overvoltage Event

Tj VDD

TSD VDDovp

TSD-THYST

VDD Abnormal
VCOMP operation

V DDon
Automatic
startup

VCOMP VDS
Not
switching

Switching

22/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Operation pictures

Figure 13. Shutdown Action Figure 14. Comp Pin Gain and Offset

VOSC

VOSChi

VOSClo
IDpeak
t

VCOMP IDlim
IDmax

Slope = 1 / HCOMP

VCOMPoff
t

ID

VCOMP
VCOMPos VCOMPovl VCOMPhi

Figure 15. Oscillator Schematic

Vcc

VDD
Rt

OSC
PWM
section

320 Ω

Ct

SOURCE

DocRev1 23/31
Operation pictures VIPer53EDIP - E / VIPer53ESP - E

The switching frequency settings shown on the graphic here below is valid within the
following boundaries:
Rt > 2kΩ
FSW = 300kHz

Figure 16. Oscillator Settings

Frequency (kHz)
300
2.2nF

4.7nF 1nF
100

10nF

22nF

10
1 10 100
RT (KΩ)

Figure 17. Typical Frequency Variation vs. Junction Temperature

Normalised Frequency

1.04

1.02

0.98

0.96

-20 0 20 40 60 80 100 120

Temperature (°C)

24/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Operation pictures

Figure 18. Typical Current Limitation vs. Junction Temperature

Normalised IDlim

1.04

1.02

0.98

0.96

-20 0 20 40 60 80 100 120

Temperature (°C)

DocRev1 25/31
Mechanical Data VIPer53EDIP - E / VIPer53ESP - E

14 Mechanical Data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

26/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Mechanical Data

Table 11. DIP8 Mechanical Data

Dimensions

Databook (mm)
Ref.
Nom. Min Max

A 5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.26
E1 6.10 6.35 7.11
e 2.54
eA 7.62
eB 10.92
L 2.92 3.30 3.81
Package Weight Gr. 470

Figure 19. Package Dimensions

DocRev1 27/31
Mechanical Data VIPer53EDIP - E / VIPer53ESP - E

Table 12. PowerSO-10 Mechanical Data

Dimensions

Databook (mm)
Ref.
Nom. Min Max
A 3.35 3.65
A1 0.00 0.10
B 0.40 0.60
c 0.35 0.55
D 9.40 9.60
D1 7.40 7.60
E 9.30 9.50
E1 7.20 7.40
E2 7.20 7.60
E3 6.10 6.35
E4 5.90 6.10
e 1.27
F 1.25 1.35
H 13.80 14.40
h 0.50
L 1.20 1.80
q 1.70
α 0° 8°

Figure 20. Package Dimensions

28/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Order codes

15 Order codes

Table 13. Order codes

Part Number Package Shipment

VIPer53ESPTR - E PowerSO-10 Tape and reel

VIPer53ESP - E PowerSO-10 Tube
VIPer53EDIP - E DIP-8 Tube

DocRev1 29/31
Revision history VIPer53EDIP - E / VIPer53ESP - E

16 Revision history

Table 14. Document revision history

Date Revision Changes

12-Jan-2006 1 Initial release.

30/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Revision history

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

© 2006 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com

DocRev1 31/31
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

STMicroelectronics:
VIPER53EDIP-E VIPER53ESPTR-E VIPER53ESP-E