a Low Cost ␮P

Supervisory Circuits
ADM705–ADM708
FEATURES FUNCTIONAL BLOCK DIAGRAMS
Guaranteed RESET Valid with VCC = 1 V
190 ␮A Quiescent Current
Precision Supply-Voltage Monitor
WATCHDOG
WATCHDOG WATCHDOG
4.65 V (ADM705/ADM707) INPUT (WDI) TRANSITION
TIMER WATCHDOG
DETECTOR OUTPUT (WDO)
4.40 V (ADM706/ADM708)
200 ms Reset Pulsewidth VCC RESET &
Debounced TTL/CMOS Manual Reset Input (MR) WATCHDOG
TIMEBASE
Independent Watchdog Timer—1.6 sec Timeout 250␮A
(ADM705/ADM706)
MR RESET
Active High Reset Output (ADM707/ADM708) GENERATOR
RESET
Voltage Monitor for Power-Fail or Low Battery VCC
Warning 4.65V*
Superior Upgrade for MAX705–MAX708 ADM705/
POWER-FAIL ADM706
Also Available in MicroSOIC Packages INPUT (PFI) POWER-FAIL
1.25V OUTPUT (PFO)
APPLICATIONS
Microprocessor Systems *VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)

Computers
Controllers
VCC
Intelligent Instruments
Critical ␮P Monitoring 250␮A RESET
Automotive Systems MR RESET RESET
Critical ␮P Power Monitoring GENERATOR
VCC
GENERAL DESCRIPTION 4.65V* ADM707/
The ADM705–ADM708 are low cost µP supervisory circuits. ADM708
POWER-FAIL
They are suitable for monitoring the 5 V power supply/battery INPUT (PFI) POWER-FAIL
OUTPUT (PFO)
and can also monitor microprocessor activity. 1.25V

The ADM705/ADM706 provide the following functions: *VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET output remains opera-
tional with VCC as low as 1 V.
Two supply-voltage monitor levels are available. The ADM705/
2. Independent watchdog timeout, WDO, that goes low if the ADM707 generate a reset when the supply voltage falls below
watchdog input has not been toggled within 1.6 seconds. 4.65 V, while the ADM706/ADM708 require that the supply
3. A 1.25 V threshold detector for power-fail warning, low fall below 4.40 V before a reset is issued.
battery detection or to monitor a power supply other than All parts are available in 8-lead DIP and SOIC packages. The
5 V. ADM707 and ADM708 are also available in space-saving
4. An active low debounced manual reset input (MR). microSOIC packages.
The ADM707/ADM708 differ in that:
1. A watchdog timer function is not available.
2. An active high reset output in addition to the active low
output is available.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
ADM705–ADM708–SPECIFICATIONS (V CC = 4.75 V to 5.5 V, TA = TMIN to TMAX unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions/Comments

VCC Operating Voltage Range 1.0 5.5 V
Supply Current 190 250 µA
Reset Threshold 4.5 4.65 4.75 V ADM705, ADM707
4.25 4.40 4.50 V ADM706, ADM708
Reset Threshold Hysteresis 40 mV
Reset Pulsewidth 160 200 280 ms
RESET Output Voltage VCC – 1.5 V ISOURCE = 800 µA
0.4 V ISINK = 3.2 mA
0.3 V VCC = 1 V, ISINK = 50 µA
0.3 V VCC = 1.2 V, ISINK = 100 µA
RESET Output Voltage VCC – 1.5 V ADM707, ADM708, ISOURCE = 800 µA
0.4 V ADM707, ADM708, ISINK = 1.2 mA
Watchdog Timeout Period (tWD) 1.00 1.60 2.25 sec
WDI Pulsewidth (tWP) 50 ns VIL = 0.4 V, VIH = VCC × 0.8
WDI Input Threshold
Logic Low 0.8 V
Logic High 3.5 V
WDI Input Current 50 150 µA WDI = VCC
–150 –50 µA WDI = 0 V
WDO Output Voltage VCC – 1.5 V ISOURCE = 800 µA
0.4 V ISINK = 1.2 mA
MR Pull-Up Current 100 250 600 µA MR = 0 V
MR Pulsewidth 150 ns
MR Input Threshold 0.8 V
2.0 V
MR to Reset Output Delay 250 ns
PFI Input Threshold 1.2 1.25 1.3 V
PFI Input Current –25 0.01 25 nA
PFO Output Voltage VCC – 1.5 V ISOURCE = 800 µA
0.4 V ISINK = 3.2 mA
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE

(TA = 25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Model Temperature Range Package Option
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V ADM705AN –40°C to +85°C N-8
Input Current ADM705AR –40°C to +85°C SO-8
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA ADM706AN –40°C to +85°C N-8
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
ADM706AR –40°C to +85°C SO-8
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW ADM707AN –40°C to +85°C N-8
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W ADM707AR –40°C to +85°C SO-8
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW ADM707ARM –40°C to +85°C RM-8
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W ADM708AN –40°C to +85°C N-8
Operating Temperature Range ADM708AR –40°C to +85°C SO-8
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C ADM708ARM –40°C to +85°C RM-8
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods of time may affect device reliability

–2– REV. B
 ADM705–ADM708
PIN FUNCTION DESCRIPTION

Pin No.
ADM705 ADM707
ADM706 ADM708
Mnemonic DIP, SOIC DIP, SPOC MicroSOIC Function
MR 1 1 3 Manual Reset Input. When taken below 0.8 V, a RESET is gener-
ated. MR can be driven from TTL, CMOS logic or from a manual
reset switch as it is internally debounced. An internal 250 µA pull-up
current holds the input high when floating.
VCC 2 2 4 5 V Power Supply Input.
GND 3 3 5 0 V. Ground reference for all signals.
PFI 4 4 6 Power-Fail Input. PFI is the noninverting input to the Power-Fail
Comparator. When PFI is less than 1.25 V, PFO goes low. If unused,
PFI should be connected to GND or VCC.
PFO 5 5 7 Power-Fail Output. PFO is the output from the Power-Fail Compara-
tor. It goes low when PFI is less than 1.25 V.
WDI 6 N/A N/A Watchdog Input. WDI is a three-level input. If WDI remains either
high or low for longer than the watchdog timeout period, the watch-
dog output WDO goes low. The timer resets with each transition at
the WDI input.
Either a high-to-low or a low-to-high transition will clear the counter.
The internal timer is also cleared whenever reset is asserted. The
watchdog timer is disabled when WDI is left floating or connected to
a three-state buffer.
NC N/A 6 8 No Connect.
RESET 7 7 1 Logic Output. RESET goes low for 200 ms when triggered. It can be
triggered either by VCC being below the reset threshold or by a low
signal on the manual reset (MR) input. RESET will remain low
whenever VCC is below the reset threshold (4.65 V in ADM705, 4.4 V
in ADM706). It remains low for 200 ms after VCC goes above the
reset threshold or MR goes from low to high. A watchdog timeout
will not trigger RESET unless WDO is connected to MR.
WDO 8 N/A N/A Logic Output. The Watchdog Output, WDO, goes low if the internal
watchdog timer times out as a result of inactivity on the WDI input. It
remains low until the watchdog timer is cleared. WDO also goes low
during low line conditions. Whenever VCC is below the reset threshold,
WDO remains low. As soon as VCC goes above the reset threshold,
WDO goes high immediately.
RESET N/A 8 2 Logic Output. RESET is an active high output suitable for systems
that use active high RESET logic. It is the inverse of RESET.

PIN CONFIGURATION
DIP, SOIC DIP, SOIC MicroSOIC

MR 1 8 WDO MR 1 8 RESET RESET 1 8 NC

ADM705/ ADM707/ RESET 2 ADM707/ 7 PFO

VCC 2 7 RESET VCC 2 7 RESET ADM708
ADM706 ADM708 MR 3 6 PFI
TOP VIEW
GND 3 TOP VIEW 6 WDI GND 3 TOP VIEW 6 NC (Not to Scale)
(Not to Scale) (Not to Scale) VCC 4 5 GND
PFI 4 5 PFO PFI 4 5 PFO
NC = NO CONNECT
NC = NO CONNECT

REV. B –3–
ADM705–ADM708
Manual Reset (ADM707/ADM708)
WATCHDOG WATCHDOG
TRANSITION
WATCHDOG
WATCHDOG
The manual reset input (MR) allows other reset sources, such as
INPUT (WDI) TIMER
DETECTOR OUTPUT (WDO) a manual reset switch, to generate a processor reset. The input
is effectively debounced by the timeout period (200 ms typical).
VCC RESET &
WATCHDOG
The MR input is TTL/CMOS compatible, so it may also be
TIMEBASE driven by any logic reset output.
250␮A

MR RESET RESET VCC VRT VRT

GENERATOR
VCC
tRS tRS
4.65V*
ADM705/
RESET
POWER-FAIL ADM706
INPUT (PFI) POWER-FAIL
OUTPUT (PFO)
1.25V

MR MR EXTERNALLY
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706) DRIVEN LOW

Figure 1. ADM705/ADM706 Functional Block Diagram

WDO

VCC
Figure 3. RESET, MR, and WDO Timing
250␮A RESET
Watchdog Timer (ADM705/ADM706)
MR
RESET RESET The watchdog timer circuit may be used to monitor the activity
GENERATOR
VCC of the microprocessor in order to check that it is not stalled in an
4.65V* ADM707/ indefinite loop. An output line on the processor is used to toggle
POWER-FAIL
ADM708 the Watchdog Input (WDI) line. If this line is not toggled
POWER-FAIL
INPUT (PFI)
OUTPUT (PFO)
within the timeout period (1.6 sec), the watchdog output
1.25V
(WDO) goes low. The WDO output may be connected to a
*VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
nonmaskable interrupt (NMI) on the processor; therefore, if the
watchdog timer times out, an interrupt is generated. The inter-
Figure 2. ADM707/ADM708 Functional Block Diagram rupt service routine should then be used to rectify the problem.
If a RESET signal is required when a timeout occurs, the WDO
CIRCUIT INFORMATION output should be connected to the manual reset input (MR).
Power-Fail RESET Output
The watchdog timer is cleared by either a high-to-low or by a
RESET is an active low output that provides a RESET signal to
low-to-high transition on WDI. It is also cleared by RESET
the Microprocessor whenever the VCC input is below the reset
going low; therefore, the watchdog timeout period begins after
threshold. An internal timer holds RESET low for 200 ms after
RESET goes high.
the voltage on VCC rises above the threshold. This is intended as
a power-on RESET signal for the microprocessor. It allows time When VCC falls below the reset threshold, WDO is forced low
for both the power supply and the microprocessor to stabilize whether or not the watchdog timer has timed out. Normally,
after power-up. The RESET output is guaranteed to remain this would generate an interrupt, but it is overridden by RESET
valid (low) with VCC as low as 1 V. This ensures that the micro- going low.
processor is held in a stable shutdown condition as the power The watchdog monitor can be deactivated by floating the
supply voltage ramps up. Watchdog Input (WDI). The WDO output can now be used as
In addition to RESET, an active high RESET output is also a low-line output since it will only go low when VCC falls below
available on the ADM707/ADM708. This is the complement of the reset threshold.
RESET and is useful for processors requiring an active high
RESET signal. tWP tWD tWD tWD
WDI

WDO

RESET RESET EXTERNALLY

TRIGGERED BY MR
tRS

Figure 4. Watchdog Timing

–4– REV. B
 ADM705–ADM708
Power-Fail Comparator
The power-fail comparator is an independent comparator that  R2 + R 3 
may be used to monitor the input power supply. The comparator’s [
VH = 1.25 1 +   R1]
 R2 × R 3 
inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.  1.25 VCC – 1.25 
VL = 1.25 + R1  – 
This input may be used to monitor the input power supply via  R2 RE 
a resistive divider network. When the voltage on the PFI input
 R1 + R2 
drops below 1.25 V, the comparator output (PFO) goes low, VMID = 1.25  
indicating a power failure. For early warning of power failure,  R2 
the comparator may be used to monitor the preregulator input
simply by choosing an appropriate resistive divider network. Valid RESET Below 1 V VCC
The PFO output can be used to interrupt the processor so that The ADM70x family of products is guaranteed to provide a
a shutdown procedure is implemented before the power is lost. valid reset level with VCC as low as 1 V; please refer to the Typi-
cal Performance Characteristics. As VCC drops below 1 V, the
INPUT internal transistor will not have sufficient drive to hold it ON so
POWER
R1
the voltage on RESET will no longer be held at 0 V. A pull-down
1.25V PFO POWER-FAIL
OUTPUT
resistor as shown in Figure 7 may be connected externally to
POWER-FAIL PFI hold the line low if it is required.
R2 INPUT ADM70x

ADM70x
Figure 5. Power-Fail Comparator
RESET
Adding Hysteresis to the Power-Fail Comparator
For increased noise immunity, hysteresis may be added to the GND R1
power-fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in Figure 7. RESET Valid Below 1 V
Figure 6. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise immu-
nity may be achieved by connecting a capacitor between PFI
and GND.

5V
7V TO 15V ADM663
INPUT POWER

VCC
R1
1.25V PFO
TO ␮P NMI
PFI
R2 ADM70x

R3

5V

PFO

0V
0V VL VH
VIN

Figure 6. Adding Hysteresis to the Power-Fail Comparator

REV. B –5–
ADM705–ADM708–Typical Performance Characteristics

VCC = 5V
TA = 25ⴗC
A! 4.50V 1.3V

VCC 100 PFI

90
1.2V

4.4V

10
0%
PFO
RESET
1V 1V 500msHo
0V

500ns/DIV

Figure 8. RESET Output Voltage vs. Supply Voltage Figure 11. PFI Comparator Deassertion Response Time

VCC = VRT
TA = 25ⴗC 5V
A1 4.50V
RESET
VCC 100 5V
90
RESET RESET

10
0%

0V
1V 1V 500msHo

0V

100ns/DIV

Figure 9. ADM707/ADM708 RESET Output Voltage vs. Figure 12. RESET, RESET Assertion
Supply Voltage

VCC = 5V VCC = VRT

5V
TA = 25ⴗC TA = 25ⴗC
RESET
1.3V 5V
PFI RESET
1.2V

5V

PFO
0V

0V 0V

500ns/DIV 100ns/DIV

Figure 10. PFI Comparator Assertion Response Time Figure 13. RESET, RESET Deassertion

–6– REV. B
 ADM705–ADM708
If, in the event of inactivity on the WDI line, a system reset is
TA = 25ⴗC required, then the WDO output should be connected to the MR
5V
VCC input as shown in Figure 16.
5V 4V

RESET RESET
ADM705/ ␮P
ADM706
WDI I/O LINE
RESET
MR WDO
GND

0V Figure 16. RESET from WDO

Monitoring Additional Supply Levels
2␮s/DIV
It is possible to use the power-fail comparator to monitor a
Figure 14. ADM705/ADM707 RESET Response Time second supply as shown in Figure 17. The two sensing resistors,
R1 and R2, are selected so that the voltage on PFI drops below
1.25 V at the minimum acceptable input supply. The PFO
APPLICATIONS output may be connected to the MR input so that a RESET is
A Typical Operating Circuit is shown in Figure 15. The unregu- generated when the supply drops out of tolerance. In this case, if
lated dc input supply is monitored using the PFI input via the either supply drops out of tolerance, a RESET will be generated.
resistive divider network. Resistors R1 and R2 should be selected
VX 5V
so that when the supply voltage drops below the desired level
(e.g., 8 V), the voltage on PFI drops below the 1.25 V threshold
VCC
thereby generating an interrupt to the µP. Monitoring the pre- RESET RESET
regulator input gives additional time to execute an orderly ADM705/
shutdown procedure before power is lost. R1 ␮P
ADM706
PFI
MR PFO
ADM666 R2
5V GND
IN GND OUT
UNREGULATED
DC
Figure 17. Monitoring 5 V and an Additional Supply, VX
VCC RESET RESET VCC
WDI I/O LINE
␮Ps With Bidirectional RESET
R1 ADM705/ In order to prevent contention for microprocessors with a bidi-
␮P
ADM706 rectional reset line, a current limiting resistor should be inserted
PFI WDO NMI between the ADM70x RESET output pin and the µP reset pin.
MR PFO INTERRUPT
R2 GND This will limit the current to a safe level if there are conflicting
output reset levels. A suitable resistor value is 4.7 kΩ. If the
MANUAL reset output is required for other uses, it should be buffered as
RESET
shown in Figure 18.

Figure 15. Typical Application Circuit 5V BUFFERED

RESET
Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software VCC

routines should toggle this line at least once every 1.6 seconds. ADM70x ␮P
If a problem occurs and this line is not toggled, WDO goes low RESET RESET
and a nonmaskable interrupt is generated. This interrupt rou-
tine may be used to clear the problem. GND GND

Figure 18. Bidirectional I-O RESET

REV. B –7–
ADM705–ADM708
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

0.39 (9.91)

C00088a–0–8/00 (rev. B)
MAX

8 5
0.25 0.31
(6.35) (7.87)
1 4
0.30 (7.62)
PIN 1 0.035 ± 0.01 REF
(0.89 ± 0.25)
0.165 ± 0.01
(4.19 ± 0.25)
0.18 ± 0.03
0.125 (3.18) (4.57 ± 0.76)
MIN
0.011 ± 0.003
0.018 ± 0.003 0.033 SEATING (4.57 ± 0.76)
0° - 15°
(0.46 ± 0.08) (0.84) PLANE
NOM
0.10 (2.54)
TYP

8-Lead SOIC
(SO-8)

0.1968 (5.00)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10)

8°
0.0500 0.0192 (0.49) 0° 0.0500 (1.27)
SEATING (1.27) 0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 0.0160 (0.41)

8-Lead MicroSOIC
(RM-8)

0.122 (3.10)
0.114 (2.90)

8 5

0.122 (3.10) 0.199 (5.05)

0.114 (2.90) 0.187 (4.75)
1
4

PRINTED IN U.S.A.
PIN 1

0.0256 (0.65) BSC

0.120 (3.05) 0.120 (3.05)
0.112 (2.84) 0.112 (2.84)
0.043 (1.09)
0.006 (0.15)
0.027 (0.68)
0.002 (0.05) 33°
0.018 (0.46) 27°
SEATING 0.011 (0.28) 0.027 (0.68)
0.008 (0.20)
PLANE 0.003 (0.08) 0.015 (0.38)

–8– REV. B