Design Report

Project – 4x4 SRAM Memory block at 45 nm technology node

A report
Submitted in fulfillment of the requirements for the award of
MICRO AND NANO DEVICE
(Electronics and communication engineering)

Submitted to
Dr. Suman Lata Tripathi

Name of Student: Jai Shivam Chaudhary

Registration Number: 12018935
Department: VLSI Design
Course name & Course Code: Micro and nano Device (ECE 166)
Email Id: jaishivam555@gmail.com
 ABSTRACT
This article describes the robust approach for designing, developing, and implementing 4 x 4
SRAM Memory block at 45 nm technology node. The project involved readings of
waveform for DC, Transient analysis along with power analysis and average power of
overall design. The design is carried out on Cadence Virtuoso. The results of various analysis
demonstrate the potential of SRAM, providing a cost-effective, reliable, and user-friendly
approach in memory design. The project highlights the importance of VLSI and various node
technologies like 18nm,32nm,45nm,90 nm etc. and its potential for continuous improvement
and innovation in this field. This project also showcases the successful integration of
electronics and software engineering to develop a memory block at 45nm technology node.
Additionally, the project emphasizes the importance of collaboration and interdisciplinary
approaches in VLSI and encourages continuous improvement and innovation in this field.
While the article describes a successful SRAM design at 45nm, it's important to consider the
challenges associated with miniaturization. Leakage currents and process variations become
more prominent at smaller technology nodes like 45nm. The article likely delves into how
the design addresses these challenges, potentially through techniques like transistor sizing
or circuit optimizations.
Overall, this project contributes to the growing body of knowledge in Micro and Nand
devices and highlights the potential for these technologies to revolutionize various
industries.

Keywords: SRAM cell, VLSI, MOSFET

 Introduction
With the advancements in technology, there is a push or urge to create high-speed, low-power
technologies like memory. A physical device called a memory module is used in digital
electronic systems to temporarily or permanently store programmes or data.In this report the
implementation of 1-bit SRAM and with its help further developed an array of 4x4 SRAM at
45nm technology node on Cadence Virtuoso[1]. In Electronics or further in VLSI(Very Large
Scale Integration) SRAM is a kind of semiconductor memory that stores each bit using a bi-
stable latching circuit and displays residual data even after multiple reads and deletion attempts,
but the memory is still volatile—that is, data is lost when the power is switched off. The basic
block of 4x4 SRAM array is 1bit SRAM which is nothing but a 6T SRAM cell. Here CMOS
technology is used for overall implementation of the 6 Transistor cell and from which its symbol
is used to design 4x4 SRAM cell array[2].

Fig 1.6T-CMOS SRAM Cell Fig 2. 4x4 SRAM Array

Here the above figure refers to the basic block fig.1 which is 1-bit 6T SRAM cell and fig.2 is 4x4
SRAM memory array designed with 6t cell.
 Components utilized in circuit.
Implementation of overall design is carried out on Cadence Virtuoso Software at 45 nm
Technology node and all the components utilized are of gdk 45 nm.
The virtually called out components are:

1.CMOS transistor (Nmos and Pmos)

Cmos or Complementary Metal-Oxide-Semiconductor is type of semiconductor technology
used to make integrated circuits (ICs). CMOS ICs are used in computers and other electronic
devices because they're low power[1], high density, and versatile.

In this project CMOS worked as basic building

block for overall design. Either 1-bit 6T SRAM cell
or the 4x4 memory array of SRAM cell,
everywhere Nmos and Pmos are used.

Fig 3. Pmos and Nmos Transistors

The combination of NMOS and PMOS transistors creates a bistable circuit. Depending on the
voltage applied to the gates of these transistors, the latch circuit can be set to either a high or
low voltage state, representing the stored data bit (1 or 0).

Fig 4. 6T SRAM cell

 NMOS transistors are primarily responsible for pulling the voltage down (data path and
enabling write operations).
 PMOS transistors contribute to pulling the voltage up (maintaining data state) and
creating a stable latch.
2. Decoder(2:4)

A decoder is a logic circuit that converts coded inputs into coded outputs, with different codes
for the input and the output. It plays a crucial role in selecting a specific memory cell within a
4x4 SRAM array. The decoder output lines are connected to the worldline(WL) (row select lines)
of the 4x4 SRAM array.

Fig 5. Gate level design for Decoder

It helps in cell selection from the array.

1. Address Decoding: The 2x4 decoder receives the two

least significant bits (A1 and A0) from the memory
address.
2. Output Activation: Based on the binary value of these
address bits, the decoder activates only one of its
output lines (D0 to D3).

3.6T SRAM Cell

A 1-bit 6T SRAM cell refers to the fundamental unit used to store a single bit (0 or 1) of data in
Static Random-Access Memory (SRAM) built with six transistors (6T).
 Fig 6. 6T SRAM Cell

Inverters: The latch circuit can be visualized as two inverters connected back-to-back, where
the output of each inverter feeds into the input of the other.
The data (0 or 1) is stored based on the voltage differential between two internal nodes of the
latch.

 A high voltage on one node and a low voltage on the other node represent a logic '1'.
 Conversely, a low voltage on one node and a high voltage on the other represent a logic
'0'

Design and Implementation

The design of array of 4x4 SRAM cell was apex and to figure it out, 1-bit SRAM cell at 45 nm
technology node has been created initially and after various parameter analysis and simulation
of it,[3] furthermore the array of 4x4 SRAM cell is designed at same gdk technology.
To design 4x4 SRAM array we have used 4 rows, and 4 columns means total 16 1-bit 6T SRAM
cell blocks and all blocks are connected and configured together and for data input across all cell
decoder has been used to take 4 different bit values in form of ‘0’ and ‘1’.
 Fig 7. Block of 6t SRAM cell

In the above fig. you can see the block diagram of 6t SRAM cell which have BL and WL as input.
Here BL means Bitline and WL means Wordline.
. Bitline (BL)

These are data lines that carry the data (0 or 1) to and from the SRAM cells.

During a read operation:

o A specific wordline is activated to select a row.

o The data stored in the cells within that row is transferred to the corresponding
bitlines.

. Wordline (WL)

 There are typically four wordlines (one for each row) in a 4x4 SRAM array.
 These are control lines that activate the transistors within a specific row of SRAM cells.
 By activating a particular wordline, we essentially enable the SRAM cells in that row to
participate in a read or write operation.
 Only the selected row's cells are connected to the bitlines during the operation, while
other rows remain isolated.

Bitlines carry the actual data (0 or 1) being read from or written to the SRAM cells.Wordlines
control which row of cells is selected for access during a read or write operation. Decoders are
often used to activate the appropriate wordline based on the memory address.
4x4 SRAM Cell

To design an array of 4x4 SRAM memory block, 6t SRAM cell symbol is used to interconnect and
configured with help of decoder to achieve the result.

Fig 8. Connection of 4x4 6t SRAM cell with 2x4 decoder to get the desired output.
The 4x4 SRAM designed using the Cadence tool is configured with specific binary values for
each row.
 The first row holds the binary value 1001
 the second row holds 1010
 the third row holds 0111
 and the fourth row holds 1101.
Selection line Values provided
Y0 1001
Y1 1010
Y2 0111
Y3 1101

This means that when a specific address is provided as input to the ROM, the corresponding
binary value stored in the ROM is outputted.

Result Analysis
a)
1.Transient response of 6t SRAM cell
`
This graph shows the transient response for 1-bit 6t SRAM cell which shows change in output Q and Qbar
according to change in WL and BL.

2.Transient response of 4x4 SRAM cell

This waveform shows the result of every row of 4x4 array and its output at particular point according to the user.
b) DC response
1. 6t SRAM cell

2. 4x4 SRAM cell

c) Average Power
4x4 SRAM cell

time (s) :pwr (W) Expression Value

0 223.3E-6 average(getData(":pwr" ?result "tran")) 194.7E-6
4.883E-15 223.3E-6
14.65E-15 223.3E-6
34.18E-15 223.4E-6
66.74E-15 223.4E-6
131.9E-15 223.5E-6
262.1E-15 223.6E-6
522.6E-15 223.8E-6
1.044E-12 224.1E-6
2.075E-12 224.9E-6
3.209E-12 237.7E-6
3.843E-12 264.5E-6
4.509E-12 298.3E-6
5.000E-12 316.7E-6
5.012E-12 316.4E-6
5.036E-12 315.7E-6
5.083E-12 314.3E-6
5.164E-12 312.0E-6
5.325E-12 307.6E-6
5.405E-12 305.7E-6
5.566E-12 302.2E-6
5.888E-12 297.0E-6
6.531E-12 294.3E-6
7.103E-12 300.0E-6

Average Power [3] : 194.7*10^-6 uW

 6t SRAM cell
time (s) :pwr (W) Expression Value
0 1.09E-06 average(getData(":pwr" ?result "tran"))
6.43E-06
9.77E-15 1.10E-06
2.93E-14 1.10E-06
6.84E-14 1.10E-06
1.45E-13 1.10E-06
2.99E-13 1.11E-06
6.06E-13 1.15E-06
1.22E-12 1.28E-06
2.45E-12 1.64E-06
3.97E-12 2.24E-06
5.72E-12 5.28E-06
6.84E-12 1.32E-05
8.26E-12 3.07E-05
9.28E-12 4.19E-05
1.00E-11 4.62E-05
1.00E-11 4.60E-05
1.01E-11 4.56E-05
1.01E-11 4.48E-05
1.03E-11 4.31E-05

Average Power: 6.43*10^-6 uW

Memory Blocks
250
194
Average Power (in uW)
200

150

100

50
6.43

0
6t SRAM 4x4 SRAM Array

Memory Blocks

Comparison of power between 1-bit SRAM and 4x4 SRAM

Advantages:
. Lower Power Consumption (compared to DRAM): While SRAM does consume power, it
generally requires less compared to DRAM due to the lack of a refresh mechanism.
. Simpler Design: SRAM's design is simpler compared to DRAM, contributing to its faster
operation.
. Speed: SRAM reigns supreme in terms of access speed. It doesn't require constant refreshing
like DRAM, making it significantly faster for data retrieval.

Conclusion
The successful implementation of this project demonstrates the capability of designing
and analysing SRAM arrays using industry-standard EDA tools Cadence Virtuoso. The
chosen 6T SRAM cell design offers a balance between simplicity, stability, and area
efficiency and using this ,4x4 SRAM memory block is implemented.

4x4 SRAM design showcase the scalability of the 1-bit SRAM and how the larger
memory blocks are tested and fabricated. With its ability to retain data without power
and its compact design, it is well-suited for various applications ranging from embedded
systems to various VLSI industry development.

Testing and analysis of the 6t SRAM and 4x4 SRAM cell had been done on parameter
like transient, DC response and also average power calculation had been recorded and
monitored through the dedicated Waveforms and schematic.

This project also highlights the importance of considering factors like technology node
scaling and its challenges. At smaller nodes like 45nm, leakage currents and process
variations become more critical and the variation in supply voltage which is 1V and 1.5V
for 45nm and 90nm technology respectively. Future work could explore techniques to
scale and stabilize these challenges and potentially investigate alternative cell designs
for further improvements in density or power consumption.
Overall, this project contributes to the ongoing advancements in VLSI memory design
and paves the way for further exploration and innovation in this field and how it can help
in development more compact and miniaturized design and products .

Reference
1)V.JEYARAMYA, D.GURUPANDI,& REKAN KUMAR S (2021). Design of 4*4 SRAM using Cadence Virtuoso
in 90nm Technology in International Research Journal of Engineering and Technology (IRJET).

2) Rudresh T K, Mallikarjun S H, & Sonu S Y(2023). Performance Evaluation of Different Topologies of

SRAM and SRAM Memory Array Design at 180nm Technology in International Journal of Engineering and
Advanced Technology (IJEAT).

3) Arijit Chakraborty, Ranjeet Singh Tomar,& Mayank Sharma (2022). Optimization of low power 12 T
SRAM bit cell using FinFET in 32 nm technology in ScienceDirect.