MPC801

High Speed CMOS ANALOG MULTIPLEXER

FEATURES
q HIGH SPEED 80ns Access Time 800ns Settling to 0.01% 250ns Settling to 0.1% q USER-PROGRAMMABLE 8-Channel Single-Ended or 4-Channel Differential q SELECTABLE TTL OR CMOS COMPATIBILITY q WILL NOT SHORT SIGNAL SOURCES Break-Before-Make Switching q SELF-CONTAINED WITH INTERNAL CHANNEL ADDRESS DECODER q 18-PIN HERMETIC DUAL-IN-LINE PACKAGE

A2 Decode A2 H L V Q H L L Q L H L VREF

DESCRIPTION
In 1A N P

The MPC801 is a high speed multiplexer that is userprogrammable for 8-channel single-ended operation or 4-channel differential operation and for TTL or CMOS compatibility. The MPC801 features a self-contained binary address decoder. It also has an enable line which allows the user to inhibit the entire multiplexer thereby facilitating channel expansion by adding additional multiplexers. High quality processing is employed to produce CMOS FET analog channel switches which have low leakage current, low ON resistance, high OFF resistance, low feedthrough capacitance, and fast settling time. Two models are available, the MPC801KG for operation from 0C to +75C.

EN A0 A1 Decoder

Out A

In 4A A2 Q A2 Decoder In 1B Q N P Out B Decoder In 4B N P N P

Input Buffer and Decoders

Multiplexer Switches Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706 Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132 PDS-464A Printed in U.S.A. October, 1993

International Airport Industrial Park Mailing Address: PO Box 11400 Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP

1985 Burr-Brown Corporation

SPECIFICATIONS
ELECTRICAL
At TA = +25C and VCC = 15V, unless otherwise noted. MPC801KG PARAMETER ANALOG INPUTS Voltage Range Maximum Overvoltage Number of Input Channels Differential Single-Ended Reference Voltage Range(1) ON Characteristics(2) ON Resistance (RON) at +25 C Over Temperature Range R ON Drift vs Temperature R ON Mismatch ON Channel Leakage Over Temperature Range ON Channel Leakage Drift OFF Characteristics OFF Isolation OFF Channel Input Leakage Over Temperature Range OFF Channel Input Leakage Drift OFF Channel Output Leakage Over Temperature Range OFF Channel Output Leakage Drift Output Leakage (All channels disabled)(3) Output Leakage with Overvoltage +16V Input 16V Input DIGITAL INPUTS Over Temperature Range TTL (4) Logic 0 (VAL) Logic 1 (VAH) IAH IAL TTL Input Overvoltage CMOS Logic 0 (VAL) Logic 1 (VAH) CMOS Input Overvoltage Address A2 Overvoltage Digital Input Capacitance Channel Select (5) Single-Ended Differential Enable POWER REQUIREMENTS Over Temperature Range Rated Supply Voltage Maximum Voltage Between Supply Pins Total Power Dissipation Allowable Total Power Dissipation(6) Supply Drain (+25 C) At 1MHz Switching Speed At 100kHz Switching Speed MIN 15 VCC 2 4 8 6 500 700
See Typical Performance Curves

TYP

MAX +15 +VCC +2

UNITS V V

10 750 1000

V nA nA

< 10 0.1 0.3

See Typical Performance Curves

50

90 0.05 0.6
See Typical Performance Curves

50

dB nA nA nA nA

0.1 0.30
See Typical Performance Curves

50

0.02 < 0.35 < 0.65

nA mA mA

0.8 2.4 0.05 4 6 1 20 6 0.3VREF 0.7VREF 2 VCC 2 5 3-bit Binary Code One of 8 2-bit Binary Code One of 4 Logic 0 Inhibits All Channels +VCC +2 +VCC +2

V V A A V V V V V pF

15 33 360 725 +14, 12.5 +12.5, 12.5

V V mW mW mA mA

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

MPC801

SPECIFICATIONS (CONT)
ELECTRICAL
At TA = +25C and VCC = 15V, unless otherwise noted. MPC801KG PARAMETER DYNAMIC CHARACTERISTICS Gain Error Crosstalk (7) TOPEN (Break-before-make delay) Access Time at +25C Over Temperature Range Settling Time(8) to 0.1% (20mV) to 0.01% (2mV) Common-Mode Rejection (Differential) DC 60Hz OFF Channel Input Capacitance, CS OFF Channel Output Capacitance, CO OFF Input to Output Capacitance, CDS TEMPERATURE MPC800KG Specification Storage MIN TYP < 0.0003
See Typical Performance Curves

MAX

UNITS % ns ns ns ns ns dB dB pF pF pF

20 80 110 250 800 > 125 > 75 1.9 10 0.02

125 150

0 65

+75 +150

C C

NOTES: (1) Reference voltage controls noise immunity, normally left open for TTL compatibility and connected to VDD for CMOS compatibility. (2) VIN = 10V, IOUT = 100A. (3) Single-ended mode. (4) Logic levels specified for VREF (pin 8) open. (5) For single-ended operation, connect output A (pin 18) to output B (pin 2) and use A2 (pin 9) as an address line. For differential operation connect A2 to VCC. (6) Derate 8mW/ C above TA = +75C. (7) 10Vp-p sine wave on all unused channels. See Typical Performance Curves. (8) For 20V step input to ON channel, into 1k load.

PIN CONFIGURATION
Top View

ORDERING INFORMATION
MODEL MPC801KG PACKAGE Cerdip TEMPERATURE RANGE 0C to +75C

+VCC Out B IN8/4B IN7/3B IN6/2B IN5/1B GND VREF A2

1 2 3 4 5 6 7 8 9

18 Out A 17 VCC 16 IN4/4A 15 IN3/3A 14 IN2/2A 13 IN1/1A 12 ENABLE 11 A0 10 A1

PACKAGE INFORMATION
MODEL MPC801KG PACKAGE 18-Pin Single-Wide Cerdip PACKAGE DRAWING NUMBER(1) 266

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.

MPC801

TYPICAL PERFORMANCE CURVES

At TA = +25C and VCC = 15V, unless otherwise noted.

CROSS TALK vs SIGNAL FREQUENCY

Cross Talk (% of OFF Channel Signal)

LEAKAGE CURRENTS vs TEMPERATURE 1000

Leakage Current (nA)

0.1

100

ON Channel OFF Output

0.01

10

0.001

OFF Input

0.0001 0.00001 100 1k 10k 100k 1M 10M Signal Frequency (Hz)

0.1 0.01 25 35 45 55 65 75 Temperature (C)

COMBINED CMR vs FREQUENCY FOR MODEL 3630 AND MPC800 140 G = 1000 120
800 1000

SETTLING TIME vs SOURCE RESISTANCE (20V Step Change, RL = 1k)

Settling Time (ns)

To 0.01% 600

CMR (dB)

100 Balanced Source 80 Unbalanced = 1k 60 Unbalanced = 10k 40 10 100 1k 10k 100k 1M Frequency (Hz)

400 To 0.1% 200 0 0 0.01 0.1 1 10 100 Source Resistance (k)

RON DRIFT vs TEMPERATURE 500

400

RON ()

300

200

100 0 25 35 45 55 65 75 Temperature (C)

MPC801

DISCUSSION OF PERFORMANCE
STATIC TRANSFER ACCURACY The static or DC transfer accuracy of transmitting the multiplexer input voltage to the output depends on the channel ON resistance (RON), the load impedance, the source impedance, the load bias current, and the multiplexer leakage current. Single-Ended Multiplexer Static Accuracy The major contributors to static transfer accuracy for singleended multiplexers are: Source resistance loading error Multiplexer ON resistance error DC offset error caused by both load bias current and multiplexer leakage current. Resistive Loading Errors The source and load impedances will determine the ON resistance loading errors. To minimize these errors: Keep loading impedance as high as possible. This minimizes the resistive loading effects of the source resistance and multiplexer ON resistance. As a guideline, load impedance of 108 or greater will keep resistive loading errors to 0.002% or less for 1000 source impedances. A 106 load impedance will increase source loading error to 0.2% or more. Use sources with impedances as low as possible. A 1000 source resistance will present less than 0.002% loading error and 10k source resistance will increase source loading error 0.02% with a 108 load impedance. Input resistive loading errors are determined by the following relationship (see Figure 1): Source and Multiplexer Resistive Loading Error (RS + RON) = RS + RON RS + RON + RL x 100%

Input Offset Voltage Bias and leakage currents generate an input offset voltage as a result of the voltage drop across the multiplexer ON resistance and source resistance. A load bias current of 10nA, a leakage current of 1nA, and an ON resistance of 700 will generate an offset voltage of 19V if a 1000 source is used, and 118V if a 10k source is used. In general, for the MPC801 the offset voltage at the output is determined by: VOFFSET = (IB + IL) (RON + RSOURCE) where: IB = Bias current of device multiplexer is driving IL = Multiplexer leakage current RON = Multiplexer ON resistance RSOURCE = Source resistance Differential Multiplexer Static Accuracy Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multiplexing low level signals with full scale ranges of 10mV to 100mV. The matching properties of the multiplexer, source and output load play a very important part in determining the transfer accuracy of the multiplexer. The source impedance unbalance, common-mode impedance, load bias current mismatch, load differential impedance mismatch, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON resistance also contribute to differential errors. Referring to Figure 2, the effects of these errors can be minimized by following the general guidelines described in this section, especially for low level multiplexing applications.
RS1A RON1A I BiasA Z Load VCC1 RCM 1 VCC4 VCC16 RS1B RS4A ILA RON1B ROFF4A ILB
CD/2

RD/2
CCM RCM

I BiasB CD/2 RD/2

where, RS = RSOURCE RL = Load resistance ROS = Multiplexer ON resistance

RS1 RON I Bias Vm VCC1 RS8 ROFF Z Load VCC8 IL Measured Voltage

RCM4

RS4B

ROFF4B

FIGURE 2. MPC801 Static Accuracy Equivalent Circuit (Differential Operation). Load (Output Device) Characteristics Use devices with very low bias current. Generally, FET input amplifiers should be used for low level signals less than 50mV FSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mV FSR. Bias current matching will determine input offset.

FIGURE 1. MPC801 Static Accuracy Equivalent Circuit (Single-ended Operation).

MPC801

 The system DC common-mode rejection (CMR) can never be better than the combined CMR of multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. Load impedances, differential and common-mode should be 1010 or higher. Source Characteristics The source impedance unbalance will produce offset, common-mode and channel-to-channel gain scatter errors. Use sources which do not have large impedance unbalances if at all possible. Keep source impedances as low as possible to minimize resistive loading errors. Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system analog common. If the MPC801 is used for multiplexing high level signals of 1V to 10V full scale ranges, the foregoing precautions should be taken, but the parameters are not as critical as for low level signal applications.
Source Node A Load

SETTLING TIME Settling time is the time required for the multiplexer to reach and maintain an output within a specified error band of its final value in response to a step input. The settling time of the MPC801 is primarily due to the channel capacitance and a combination of resistances which include the source and load resistances. If the parallel combination of the source and load resistance times the total channel capacitance is kept small, then the settling time is primarily affected by internal RCs. For the MPC801, the internal capacitance is approximately 10pF differential or 20pF single-ended. With external capacitance neglected, the time constant of source resistance in parallel with load resistance and the internal capacitance should be kept less than 40ns. This means the source resistance should be kept to less than 4k (assume high load resistance) to maintain fast settling times. ACCESS TIME This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10V signal change between channels. CROSSTALK Crosstalk is the amount of signal feedthrough from the 3 differential or 7 signal-ended OFF channels appearing at the multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel. OFF resistance, and junction capacitances in series with the RON and RSOURCE impedances of the ON channel. Crosstalk is measured with

CS RSOURCE

CLOAD

RLOAD

FIGURE 3. Settling Time Effects (Single-ended).

RSA CSA RCMS Source CCMS RSB CSB Node B Load RDB CDB

Node A RDA CDA

FIGURE 4. Settling and Common-Mode Effects (Differential).

MPC801

a 20Vp-p, 1000Hz sine wave applied to all OFF channels. The crosstalk for these multiplexers is shown in the Typical Performance Curves. COMMON-MODE REJECTION (Differential Mode Only) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CMR is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. Protection is provided for commonmode signals of 2V above the power supply voltages with no damage to the analog switches. The CMR of the MPC801 and Burr-Browns model 3630 instrumentation amplifier is 120dB at DC to 10Hz with a 6dB/octave rolloff to 80dB at 1000Hz. This measurement of CMR is shown in the Typical Performance Curves and is made with a Burr-Brown model 3630 instrumentation amplifier connected for a gain of 1000 and with source unbalance of 10k, 1k and no unbalance. Factors which will degrade multiplexer and system DC CMR are: Amplifier bias current and differential impedance mismatch. Load impedance mismatch. Multiplexer impedance and leakage current mismatch. Load and source common-mode impedance. AC CMR rolloff is determined by the amount of commonmode capacitances (absolute and mismatch) from each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and multiplexer to amplifier wiring must be minimized. Use twisted-shielded pair signal lines wherever possible.

common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as close as possible to system analog common or to the common-mode guard driver. LOGIC LEVELS The logic level is user-programmable as either TTL-compatible by leaving the VREF (pin 8) open, or CMOS-compatible by connecting the VREF to VDD (CMOS supply voltage). 16-CHANNEL SINGLE-ENDED OPERATION To use the MPC801 as a 8-channel single-ended multiplexer, output A (pin 18) is connected to output B (pin 2) to form a single output, then all three address lines (A0, A1 and A2 ) are used to address the correct channel. The MPC801 can also be used as a dual channel singleended multiplexer by not connecting output A and B, but then only one channel in one of the multiplexers can be addressed at a time. 8-CHANNEL DIFFERENTIAL OPERATION To use the MPC801 as an 4-channel differential multiplexer, connect address line A2 to VCC then use the remaining two address lines (A0, and A1) to address the correct channel. The differential inputs are the pairs of A1 and B1, A2 and B2, etc. TRUTH TABLES MPC801 used as an 8-channel single-ended multiplexer or 4-channel dual multiplexer.
USE A2 AS DIGITAL ADDRESS INPUT ENABLE L H H H A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H ON CHANNEL TO OUT A None 1A 2A 3A 4A None None None None OUT B None None None None None 1B 2B 3B 4B

INSTALLATION AND OPERATING INSTRUCTIONS

The ENABLE input, pin 12, is included for expansion of the number of channels on a single-node as illustrated in Figure 5. With the ENABLE line at a logic 1, the channel is selected by the Channel Select Address (shown in the Truth Tables). If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the ENABLE line is not to be used, simply tie it to logic 1. For the best settling time, the input wiring and interconnections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pullup resistors are recommended. To preserve common-mode rejection of the MPC801, use twisted-shielded pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help

H H H H H

For 8-channel single-ended function, tie out A to out B, for dual 4-channel function use the A2 address pin to select between MUX A and MUX B, where MUX A is selected with A2 low.

MPC801 used as a 4-channel differential multiplexer.

A2 CONNECT TO VCC ENABLE L H H H H A1 X L L H H A0 X L H L H ON CHANNEL TO OUT A None 1A 2A 3A 4A OUT B None 1B 2B 3B 4B

MPC801

CHANNEL EXPANSION Single-Tier Expansion Up to eight MPC801s can be connected to a single node to form a 64-channel single-ended multiplexer, or up to eight MPC801s can be connected to two nodes to form a 32-channel differential multiplexer. Programming is accomplished with a 6-bit address and a 1-of-8 decoder (see Figure 5). The decoder drives the enable inputs of the MPC801 turning on only one multiplexer at a time. Two-Tier Expansion Up to nine MPC801s can be connected in a two-tier structure to form a 64-channel single-ended multiplexer (see Figure

6), or up to five MPC801s can be connected in a two-tier structure to form a 16-channel differential multiplexer. Programming is accomplished with a 6-bit address. SINGLE VS MULTITIERED CHANNEL EXPANSION In addition to reducing programming complexity, two-tier configuration offers the added advantages over single-node expansion of reduced OFF channel current leakage (reduced Offset), better CMR, and a more reliable configuration if a channel should fail in the ON condition (short). Should a channel fail ON in the single-node configuration, data cannot be taken from any channel, whereas only one-channel group is failed (4 or 8) in the multitiered configuration.

6-Bit Channel Address Generator

6-Bit Channel Address Generator

8 Analog Inputs

8 Analog Inputs

In1 In2 In3

A 0 A 1 A2

1 of 8 Decoder

In1 In2 In3

A0 A1 A2

MPC801 Enable Out A Out B

Multiplexer Output

MPC801 Enable Out A Out B A 1 A2 A3 In1 In2 In3 MPC801 Enable Out A Out B Multiplexer Output MPC801 Enable Out A Out B

In8

In8

8 Analog Inputs

MPC801 Enable Out A Out B

8 Analog Inputs

In1 In2 In3

A 0 A 1 A2

In1 In2 In3

A0 A1 A2

In8

In8

In8

To multiplexers 3 - 8

To multiplexers 3 - 8

FIGURE 5. 64-channel, Single-tier, Single-ended Expansion.

FIGURE 6. 64-channel, Two-tier, Single-ended Expansion.

MPC801