HT6751A/B
Camera Motor Driver (1.5 Channel)
Features
·       Operating voltage: 2.0V~6.0V                                                         ·   Built-in thermal shutdown circuit
·       Operating current < 2mA at 3.0V, No load                                             ·   Built-in H bridge control circuit
·       Standby current IVDD< 2mA, no load                                                   ·   Built-in spark killer diode
·       Separate logic power supply and motor                                                ·   Provides strong ESD (min. of 4KV) per pin
        power supply                                                                         ·   8-pin SOP package
Applications
·       Camera motor driver                                                                  ·   Toy motor driver
General Description
The IC can control H Bridge circuit for motor                                                verse function/Brake function/Stop function for
driving. It provides Spark Killer Diode/Ther-                                                motor driver application. It is designed by LSI
mal Shutdown function/Forward function/Re-                                                   high technology with low power process.
Block Diagram
                             R C                     C h a rg e
    V D D               O s c illa to r               P u m p
    V S S
                                                                           H B r id g e           V M
                                                                         M o to r D r iv e        O U T 1
     IN 1                                             T h e rm a l           C ir c u it
                            In p u t                                                              O U T 2
     IN 2                                           S h u td o w n
                          C o n tro l
     IN 3                                               C ir c u it
Pin Assignment
            V M     1                8    O U T 2
     O U T 1        2                7    IN 2
            IN 3    3                6    V D D
       V S S        4                5    IN 1
                   H T 6 7 5 1 A /B
                        8 S O P
                                                                                         1                                      August 7, 2000
                   This datasheet has been downloaded from http://www.digchip.com at this page
                                                                                                 HT6751A/B
Pin Description
  Pin No.       Pin Name          I/O                                   Description
       1        VM                 P     Power of motor driving circuit
       2        OUT1               O     Connect to motor terminal
       3        IN3                I     Input signal
       4        VSS               ¾      Negative power supply, ground
       5        IN1                I     Input signal
       6        VDD               ¾      Positive power supply
       7        IN2                I     Input signal
       8        OUT2               O     Connect to motor terminal
Absolute Maximum Ratings
Supply Voltage .......................VDD-0.3V to 7.0V          Storage Temperature.................-40°C to 125°C
Voltage to Input Terminal .....-0.3V to VDD+0.3                 Operating Temperature ..............-20°C to 85°C
Junction Temperature ..............................150°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
      mum Ratings² may cause substantial damage to the device. Functional operation of this de-
      vice at other conditions beyond those listed in the specification is not implied and prolonged
      exposure to extreme conditions may affect device reliability.
Electrical Characteristics                                                                               Ta=25°C
                                                      Test Conditions
 Symbol                Parameter                                                  Min.    Typ.    Max.     Unit
                                                VDD            Conditions
 VDD         Operating Voltage 1                  ¾                ¾               2.0     ¾       6.0       V
 VM          Operating Voltage 2                  ¾    Motor loading               1.8     ¾       6.0       V
 IVM         VM Current                                Standby mode with
                                                 5V                                ¾       ¾        10      mA
                                                       internal pump
 IOPR        Operating Current                   5V    No load @ VDD=5V            ¾       ¾        2       mA
 IVDD        Standby Current                     5V    Standby mode                ¾        1       2       mA
 IIL         Input Leakage Current               5V    0<Vin<VDD                  -1.0     ¾       1.0      mA
 VIL         Input Low Voltage                   5V                ¾              -0.3           0.3VDD      V
 VIH         Input High Voltage                  5V                ¾             0.6VDD    ¾     VDD+0.3     V
 RON                                                   (up_NMOS+down_
             H Bridge On Resistance              3V                                ¾       ¾       0.4       W
                                                       NMOS) at 3V
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                                                                                      HT6751A/B
                                                Test Conditions
 Symbol            Parameter                                           Min.   Typ.     Max.    Unit
                                         VDD           Conditions
 tCP_ON     Charge Pump Turn On                  VDD=VM=5V,
                                           5V                           ¾      ¾         2      ms
            Time                                 Ivm=0.5A
 tCP_OFF    Charge Pump Turn Off                 VDD=VM=5V,
                                           5V                           ¾      ¾         1      ms
            Time                                 Ivm=0.5A
 tH_ON                                           VDD=VM=5V,
            H Bridge Turn On Time          5V                           ¾      ¾        10       ms
                                                 Ivm=0.5A
 tH_OFF                                          VDD=VM=5V,
            H Bridge Turn Off Time         5V                           ¾      ¾         5       ms
                                                 Ivm=0.5A
Functional Description
· In HT6751A function
  IN1      IN2     IN3          Function                    MOS On                   MOS Off
   0        1         1    Motor1 forward                    P1/N2                    P2/N1
   1        0         1    Motor1 reverse                    P2/N1                    P1/N2
   0        0         1    Motor1 brake                      N1/N2                    P1/P2
   1        1         1    Standby mode                        ¾                P1/P2/N1/N2
   0        1         0    Motor2 forward                    P2/(N3)                 N2/(P3)
   1        0         0    Motor2 reverse                    N2/(P3)                 P2/(N3)
   0        0         0    Motor2 brake                      N2/(N3)                 P2/(P3)
· In HT6751B function
 IN1       IN2   IN3           Function                    MOS On                    Mos Off
   1        0     0       Motor1 forward                    P1/N2                    P2/N1
   0        1     0       Motor1 reverse                    P2/N1                    P1/N2
   1        1     0       Motor1 brake                      N1/N2                     P1/P2
   0        0     0       Standby mode                        ¾                 P1/P2/N1/N2
   1        0     1       Motor2 forward                    P2/(N3)                  N2/(P3)
   0        1     1       Motor2 reverse                    N2/(P3)                  P2/(N3)
   1        1     1       Motor2 brake                      N2/(N3)                  P2/(P3)
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                                                                                                                                                                              HT6751A/B
 ¨   In normal state and standby mode                                                                                   ¨   The system enters thermal shutdown mode
     – Charge pump circuit is in off state                                                                                  (current is limited below 500mA) when the
     – Oscillator circuit is in off state                                                                                   temperature of the internal sensor is
     – Standby current is below 2mA
                                                                                                                            greater than Junction Temperature and
                                                                                                                            then release this mode until the tempera-
     – For HT6751A, the oscillator circuit and
                                                                                                                            ture of the internal sensor below (Junction
       charge pump circuit is on until IN1 or IN2                                                                           Temperatue >150°C). The system can ac-
       or IN3 is low input                                                                                                  cept IN1/IN2/IN3 signal when in thermal
     – For HT6751B, the oscillator circuit and
                                                                                                                            shutdown mode.
       charge pump circuit is on until IN1 or IN2
       or IN3 is high input
Application Circuits
                                                                                                                                                                   V    D D        V    M
                                          V    D D                V           M
                                  V D D                   V M                                                                            F o rw a rd              V D D           V M
                                  IN 1                O U T 1                                                                                                     IN 1         O U T 1
     1 C h a n n e l                                                                                                                     R e v e rs e                                           M
                                                                                  M 1                                       B ra k e
          fo r                                                                                                                                                    IN 2         O U T 2
      m C /A S IC                 IN 2                O U T 2
                       V   D D                                                                                                                          V   D D
                                  IN 3                  V S S                                                                                                     IN 3           V S S
                                              H T 6 7 5 1 A                                                                                                            H T 6 7 5 1 A
                                                                                                                                                                   V    D D        V    M
                                  V            D D        V           M
                                  V D D                  V M                                                                           F o rw a rd                V D D           V M
                                  IN 1                O U T 1                                                                                                     IN 1         O U T 1
  1 C h a n n e l                                                                                                                      R e v e rs e
                                                                                  M 1                                                                                                       M
       fo r                                                                                                                 B ra k e
   m C /A S IC                    IN 2                O U T 2                                                                                                     IN 2         O U T 2
                                  IN 3                  V S S                                                                                                     IN 3           V S S
                                          H T 6 7 5 1 B                                                                                                                H T 6 7 5 1 B
                                      V        D D            V           M
                                                                                                  P 3
                                  V D D                  V M
                                  IN 1                O U T 1                           O U T 3
                                                                                                        E x te rn a l
 1 .5 C h a n n e l                                                               M 1   M 2       N 3
        fo r
    m C /A S IC                   IN 2                O U T 2
                                  IN 3                  V S S
                                 H T 6 7 5 1 A /B
                                                                                                          4                                                                    August 7, 2000
                                                                                                      HT6751A/B
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Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
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