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SEMICONDUCTOR TECHNICAL DATA by MLP1N06CL/D

SMARTDISCRETES 
Internally Clamped, Current Limited
MLP1N06CL
Motorola Preferred Device

N–Channel Logic Level Power MOSFET

These SMARTDISCRETES devices feature current limiting for short circuit
VOLTAGE CLAMPED
protection, an integral gate–to–source clamp for ESD protection and gate–to–drain
CURRENT LIMITING
clamp for over–voltage protection. No additional gate series resistance is required
MOSFET
when interfacing to the output of a MCU, but a 40 kΩ gate pulldown resistor is
62 VOLTS (CLAMPED)
recommended to avoid a floating gate condition.
RDS(on) = 0.75 OHMS
The internal gate–to–source and gate–to–drain clamps allow the devices to be
applied without use of external transient suppression components. The gate–to–
source clamp protects the MOSFET input from electrostatic gate voltage stresses
up to 2.0 kV. The gate–to–drain clamp protects the MOSFET drain from drain D
avalanche stresses that occur with inductive loads. This unique design provides
voltage clamping that is essentially independent of operating temperature.
The MLP1N06CL is fabricated using Motorola’s SMARTDISCRETES technolo-
gy which combines the advantages of a power MOSFET output device with
on–chip protective circuitry. This approach offers an economical means for
R1
providing additional functions that protect a power MOSFET in harsh automotive
G
and industrial environments. SMARTDISCRETES devices are specified over a
wide temperature range from –50°C to 150°C.
• Temperature Compensated Gate–to–Drain Clamp Limits Voltage Stress
Applied to the Device and Protects the Load From Overvoltage R2
• Integrated ESD Diode Protection
• Controlled Switching Minimizes RFI
S
• Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit
Drain–to–Source Voltage VDSS Clamped Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR Clamped Vdc
Gate–to–Source Voltage — Continuous VGS ±10 Vdc
Drain Current — Continuous ID Self–limited Adc
Drain Current — Single Pulse IDM 1.8
Total Power Dissipation PD 40 Watts
Electrostatic Discharge Voltage (Human Body Model) ESD 2.0 kV
G
Operating and Storage Junction Temperature Range TJ, Tstg –50 to 150 °C D
S
THERMAL CHARACTERISTICS
Thermal Resistance, Junction to Case RθJC 3.12 °C/W
Thermal Resistance, Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes, TL 260 °C
1/8″ from case CASE 221A–06, Style 5
TO–220AB
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS
Single Pulse Drain–to–Source Avalanche Energy EAS 80 mJ
(Starting TJ = 25°C, ID = 2.0 A, L = 40 mH) (Figure 6)

SMARTDISCRETES is a trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS
Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1
 MLP1N06CL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Sustaining Voltage (Internally Clamped) V(BR)DSS Vdc
(ID = 20 mA, VGS = 0) 59 62 65
(ID = 20 mA, VGS = 0, TJ = 150°C) 59 62 65
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 45 V, VGS = 0) — 0.6 5.0
(VDS = 45 V, VGS = 0, TJ = 150°C) — 6.0 20
Gate–Body Leakage Current IGSS µAdc
(VG = 5.0 V, VDS = 0) — 0.5 5.0
(VG = 5.0 V, VDS = 0, TJ = 150°C) — 1.0 20

ON CHARACTERISTICS*
Gate Threshold Voltage VGS(th) Vdc
(ID = 250 µA, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µA, VDS = VGS, TJ = 150°C) 0.6 — 1.6
Static Drain–to–Source On–Resistance RDS(on) Ohms
(ID = 1.0 A, VGS = 4.0 V) — 0.63 0.75
(ID = 1.0 A, VGS = 5.0 V) — 0.59 0.75
(ID = 1.0 A, VGS = 4.0 V, TJ = 150°C) — 1.1 1.9
(ID = 1.0 A, VGS = 5.0 V, TJ = 150°C) — 1.0 1.8
Forward Transconductance (ID = 1.0 A, VDS = 10 V) gFS 1.0 1.4 — mhos
Static Source–to–Drain Diode Voltage (IS = 1.0 A, VGS = 0) VSD — 1.1 1.5 Vdc
Static Drain Current Limit ID(lim) A
(VGS = 5.0 V, VDS = 10 V) 2.0 2.3 2.75
(VGS = 5.0 V, VDS = 10 V, TJ = 150°C) 1.1 1.3 1.8

RESISTIVE SWITCHING CHARACTERISTICS*

Turn–On Delay Time td(on) — 1.2 2.0 µs
Rise Time (VDD = 25 V, ID = 1.0 A, tr — 4.0 6.0
Turn–Off Delay Time VGS = 5.0 V, RG = 50 Ohms) td(off) — 4.0 6.0
Fall Time tf — 3.0 5.0
* Indicates Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

4
TJ = 25°C VDS ≥ 7.5 V
4 –50°C
ID , DRAIN CURRENT (AMPS)
ID , DRAIN CURRENT (AMPS)

3
10 V
6V 8V 3
4V 25°C
2
2

1 VGS = 3 V TJ = 150°C
1

0 0
0 2 4 6 8 0 2 4 6 8
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. Output Characteristics Figure 2. Transfer Function

2 Motorola TMOS Power MOSFET Transistor Device Data

 MLP1N06CL
THE SMARTDISCRETES CONCEPT
From a standard power MOSFET process, several active 4
and passive elements can be obtained that provide on–chip VGS = 5 V

ID(lim) , DRAIN CURRENT (AMPS)

protection to the basic power device. Such elements require VDS = 7.5 V
only a small increase in silicon area and/or the addition of one 3
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
as system cost reduction. The SMARTDISCRETES device
2
functions can now provide an economical alternative to smart
power ICs for power applications requiring low on–resistance,
high voltage and high current.
These devices are designed for applications that require a 1
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit
(MCU). Ideal applications include automotive fuel injector 0
–50 0 50 100 150
driver, incandescent lamp driver or other applications where
TJ, JUNCTION TEMPERATURE (°C)
a high in–rush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE Figure 3. ID(lim) Variation With Temperature
The amount of time that an unprotected device can with-
stand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the de- 4
vice, its initial junction temperature, and the supply voltage. ID = 1 A

R DS(on), ON–RESISTANCE (OHMS)

Without some form of current limiting, a shorted load can
raise a device’s junction temperature beyond the maximum
3
rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLP1N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature 2
150°C
is under 100°C. For longer periods of operation in the cur- 25°C
TJ = –50°C
rent–limited mode, device heatsinking can extend operation
from several seconds to indefinitely depending on the 1
amount of heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
0
TEMPERATURE 0 2 4 6 8 10
The on–chip circuitry of the MLP1N06CL offers an inte- VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
grated means of protecting the MOSFET component from
high in–rush current or a shorted load. As shown in the sche- Figure 4. RDS(on) Variation With
matic diagram, the current limiting feature is provided by an Gate–To–Source Voltage
NPN transistor and integral resistors R1 and R2. R2 senses
the current through the MOSFET and forward biases the
NPN transistor’s base as the current increases. As the NPN
turns on, it begins to pull gate drive current through R1, drop-
ping the gate drive voltage across it, and thus lowering the 1.25
voltage across the gate–to–source of the power MOSFET ID = 1 A
and limiting the current. The current limit is temperature de-
RDS(on), ON–RESISTANCE (OHMS)

pendent as shown in Figure 3, and decreases from about 2.3 1

Amps at 25°C to about 1.3 Amps at 150°C.
Since the MLP1N06CL continues to conduct current and VGS = 4 V
dissipate power during a shorted load condition, it is impor- 0.75
tant to provide sufficient heatsinking to limit the device junc-
VGS = 5 V
tion temperature to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms 0.5
to the power MOSFET’s on–resistance, but the effect of tem-
perature on the combination is less than on a standard
MOSFET due to the lower temperature coefficient of R2. The 0.25
on–resistance variation with temperature for gate voltages of –50 0 50 100 150
4 and 5 Volts is shown in Figure 5. TJ, JUNCTION TEMPERATURE (°C)
Back–to–back polysilicon diodes between gate and source Figure 5. On–Resistance Variation With
provide ESD protection to greater than 2 kV, HBM. This on– Temperature
chip protection feature eliminates the need for an external
Zener diode for systems with potentially heavy line transients.

Motorola TMOS Power MOSFET Transistor Device Data 3

MLP1N06CL

BV(DSS) , DRAIN–SOURCE SUSTAINING VOLTAGE (VOLTS)

WAS , SINGLE PULSE AVALANCHE ENERGY (mJ) 100 64

80
63

60
62
40

61
20

0 60
25 50 75 100 125 150 –50 0 50 100 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Single Pulse Avalanche Energy Figure 7. Drain–Source Sustaining

versus Junction Temperature Voltage Variation With Temperature

FORWARD BIASED SAFE OPERATING AREA DUTY CYCLE OPERATION

The FBSOA curves define the maximum drain–to–source When operating in the duty cycle mode, the maximum
voltage and drain current that a device can safely handle drain voltage can be increased. The maximum operating
when it is forward biased, or when it is on, or being turned on. temperature is related to the duty cycle (DC) by the following
Because these curves include the limitations of simultaneous equation:
high voltage and high current, up to the rating of the device, TC = (VDS x ID x DC x RθCA) + TA
they are especially useful to designers of linear systems. The
The maximum value of VDS applied when operating in a
curves are based on a case temperature of 25°C and a maxi-
duty cycle mode can be approximated by:
mum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by 150 – TC
VDS =
using the thermal response curves. Motorola Application ID(lim) x DC x RθJC
Note, AN569, “Transient Thermal Resistance — General
Data and Its Use” provides detailed instructions. 10
6
I D , DRAIN CURRENT (AMPS)

3 ID(lim) – MAX 1 ms
MAXIMUM DC VOLTAGE CONSIDERATIONS 1.5
2 ms
The maximum drain–to–source voltage that can be contin- ID(lim) – MIN 5 ms
uously applied across the MLP1N06CL when it is in current dc
1
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maxi- 0.6
DEVICE/POWER LIMITED
mum rated operating temperature (1.8 A at 150°C) and not RDS(on) LIMITED
0.3
the RDS(on). The maximum voltage can be calculated by the VGS = 5 V
0.2
following equation: SINGLE PULSE
TC = 25°C
0.1
(150 – TA) 1 2 3 6 10 20 30 60 100
Vsupply =
ID(lim) (RθJC + RθCA) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

where the value of RθCA is determined by the heatsink that is Figure 8. Maximum Rated Forward Bias
being used in the application. Safe Operating Area (MLP1N06CL)

4 Motorola TMOS Power MOSFET Transistor Device Data

 MLP1N06CL
1.0
0.7 D = 0.5
RθJC(t) = r(t) RθJC
r(t), EFFECTIVE TRANSIENT THERMAL 0.5 RθJC(t) = 3.12°C/W Max
RESISTANCE (NORMALIZED)
0.3 0.2 D Curves Apply for Power
0.2 Pulse Train Shown
0.1 Read Time at t1
TJ(pk) – TC = P(pk) RθJC(t)
0.1 0.05
0.07 0.02
0.05 P(pk)

0.03
0.01 t1
0.02 t2
SINGLE PULSE DUTY CYCLE, D =t1/t2
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME (ms)

Figure 9. Thermal Response (MLP1N06CL)

VDD ton toff

RL Vout td(on) tr td(off) tf

90% 90%

Vin DUT
PULSE GENERATOR OUTPUT, Vout
z = 50 Ω 10%
Rgen INVERTED
50Ω
90%
50 Ω
50% 50%
INPUT, Vin PULSE WIDTH
10%

Figure 10. Switching Test Circuit Figure 11. Switching Waveforms

ACTIVE CLAMPING
SMARTDISCRETES technology can provide on–chip real- elements provide greater than 2.0 kV electrostatic voltage
ization of the popular gate–to–source and gate–to–drain protection.
Zener diode clamp elements. Until recently, such features The avalanche voltage of the gate–to–drain voltage clamp
have been implemented only with discrete components is set less than that of the power MOSFET device. As soon
which consume board space and add system cost. The as the drain–to–source voltage exceeds this avalanche volt-
SMARTDISCRETES technology approach economically age, the resulting gate–to–drain Zener current builds a gate
melds these features and the power chip with only a slight voltage across the gate–to–source impedance, turning on
increase in chip area. the power device which then conducts the current. Since vir-
In practice, back–to–back diode elements are formed in a tually all of the current is carried by the power device, the
polysilicon region monolithicly integrated with, but electrically
gate–to–drain voltage clamp element may be small in size.
isolated from, the main device structure. Each back–to–back
This technique of establishing a temperature compensated
diode element provides a temperature compensated voltage
drain–to–source sustaining voltage (Figure 7) effectively re-
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free moves the possibility of drain–to–source avalanche in the
from direct interaction with the conduction regions of the power device.
power device, thus eliminating parasitic electrical effects The gate–to–drain voltage clamp technique is particularly
while maintaining excellent thermal coupling. useful for snubbing loads where the inductive energy would
To achieve high gate–to–drain clamp voltages, several otherwise avalanche the power device. An improvement in
voltage elements are strung together; the MLP1N06CL uses ruggedness of at least four times has been observed when
8 such elements. Customarily, two voltage elements are inductive energy is dissipated in the gate–to–drain clamped
used to provide a 14.4 volt gate–to–source voltage clamp. conduction mode rather than in the more stressful gate–to–
For the MLP1N06CL, the integrated gate–to–source voltage source avalanche mode.

Motorola TMOS Power MOSFET Transistor Device Data 5

MLP1N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS

The MLP1N06CL has been designed to allow direct inter- VBAT

face to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a VDD
40 kΩ gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The in-
ternal clamps allow the device to be used without any exter- D
nal transistent suppressing components.
G
MCU MLP1N06CL

PACKAGE DIMENSIONS

NOTES:
SEATING STYLE 5: 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE PIN 1. GATE Y14.5M, 1982.
2. DRAIN 2. CONTROLLING DIMENSION: INCH.
B F C 3. SOURCE 3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S 4. DRAIN BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
1 2 3 B 0.380 0.405 9.66 10.28
U C 0.160 0.190 4.07 4.82
H D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
K G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04
CASE 221A–06
ISSUE Y

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MLP1N06CL/D*
6 ◊ Motorola TMOS Power MOSFET Transistor Device Data
MLP1N06CL/D