Acknowledgement

The slides used in this lecture are taken for academic purpose only.
The resources are taken from:
1. CMOS VLSI Design: A Circuit and Systems Perspective, by Neil
Weste, David Money Harris, 4th ed., Addison Wesley, 2011
2. CMOS Digital Integrated Circuits: Analysis and Design, Sung-Mo
(Steve) Kang and Yusuf Leblebici, 2nd ed., McGraw Hill, 2003
Combinational CMOS Logic Circuits
 Combinational vs. Sequential Logic

In Combinational Out
Combinational
In Logic Out Logic
circuit circuit

State

Combinational Sequential
The output is determined only by The output is determined by
• Current inputs • Current inputs
• Previous inputs

Output = f(In) Output = f(In, Previous In)

 CMOS Combinational Logic
VDD

In1
In2 pMOS
Network Pull Up Network (PUN)
InN
f(In1,In2,…InN)
In1
In2 nMOS
Network Pull Down Network (PDN)
InN

PUN and PDN are dual logic networks

• The complementary operation of a CMOS gate

❖ The nMOS network (PDN) is on and the pMOS network (PUN) is off
❖ The pMOS network is on and the nMOS network is off.
 NMOS Transistors Series/Parallel
Connection

❖ Transistors can be thought as a switch controlled by its gate signal

❖ NMOS switch closes when switch control input is high

A B

Y = X if A and B=AB
X Y

X B Y = X if AOR B=A+B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

 PMOS Transistors Series/Parallel
Connection

❖ PMOS switch closes when switch control input is low.

A B

X
Y = X if A AND B = A+B
Y
A

X B
Y Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

 Threshold Drops

VDD VDD
PUN
S D
VDD

D 0 → VDD VGS
S 0 → VDD - VTn
CL CL

PDN VDD → 0 VDD → |VTp|

VGS
D CL S CL
VDD

S D
 CMOS 2-Input NOR Gate
❖ The transistor level implementation for the NOR gate is:
 CMOS 2-Input NOR Gate

PMOS Pull-Up Network

❖ The only time the pull-up network drives the output is when we have two 0’s on
the inputs.
❖ Since the pull-up network uses PMOS transistors (0 = ON), we can say
that the pull-up network is conducting if VA AND VB are 0.

❖ This implies a series configuration in the pull-up (PMOS) network.

NMOS Pull-Down Network

❖ The pull-down network drives the output continually unless VA AND VB are 0.
❖ Since the pull-down network uses NMOS transistors (1 = ON), we can say that
the pull-down network is conducting if VA OR VB are 1.

❖ This implies a parallel configuration in the pull-down (NMOS) network.

 CMOS 2-Input NOR Gate
❖ The critical voltages for an inverter Vth can be adjusted with the sizing of the
transistors

❖ More complex logic gate can be analysed by converting it into an equivalent inverter

Transistors in Series
❖ The current flowing in series transistors needs to go through two channels,
each with an equivalent resistance (or transconductance k)

❖ With the effective resistance doubling, the transconductance (or the

ability to drive a current given an input voltage) is divided by 2

❖ Transistors
in series with the same size can be modeled as an equivalent transistor
with keq=k/2

Transistors in Parallel
❖ The current flowing in parallel transistors can conduct twice the amount of
current compared to a a single transistor with the same gate voltage.

❖ We can model this behavior with an equivalent transistor with keq=2∙k

 CMOS 2-Input NOR Gate

❖ We can model a 2-Input NOR gate as an equivalent inverter as follows:

❖ let’s use representative voltages of VDD=5 V and Vth= 2.5 to illustrate the derivation
CMOS 2-Input NOR Gate
CMOS 2-Input NOR Gate
CMOS 2-Input NOR Gate
CMOS 2-Input NOR Gate
CMOS 2-Input NOR Gate
 CMOS 2-Input NOR Gate
Now compare this expression with the switching threshold voltage of the CMOS inverter
CMOS 2-Input NOR Gate: Equivalent Inverter approach

❖ The switching threshold voltage of the NOR2 gate using the equivalent-
inverter approach. When both inputs are identical, the parallel-connected
nMOS transistors can be represented by a single nMOS transistor with 2kn.
and the series-connected pMOS transistors are represented by a single
pMOS transistor with kP/2.
CMOS 2-Input NOR Gate: Equivalent Inverter approach

❖ Using the inverter switching threshold expression for the equivalent

inverter circuit of NOR2 gate, we obtain
 CMOS N-Input NOR Gate
❖ To expand the NOR gate to N-inputs,
❖ Add more PMOS transistors in series in the Pull-up Network
❖ Add more NMOS transistors in parallel in the Pull-down Network

B Output

B A

GND GND
 CMOS N-Input NOR Gate

❖ Our V th expression for an N-input NOR gate becomes:

❖ The rule of thumb for an ideal symmetric equivalent inverter becomes:

CMOS 2-Input NOR Gate Layout
 CMOS 2-Input NAND Gate

❖ The truth table for a 2-input NAND gate is:

 CMOS 2-Input NAND Gate
❖ We can model the 2-Input NAND gate as an equivalent invert as follows:
 CMOS 2-Input NAND Gate

❖ The switching threshold for the 2-input NAND gate is:

 CMOS 2-Input NAND Gate
❖ In an equivalent inverter model, to get V th =V DD/2, we set VT,n = VTP :

❖ The NMOS series network has to be sized larger in order to overcome the voltage drop
across each series stage.
 CMOS N-Input NAND Gate

❖ To expand the NAND gate, we

❖ Add more PMOS transistors in parallel in the Pull-up Network

❖ Add more NMOS transistors in series in the Pull-down Network

V V
DD DD

A B

Output

B
 CMOS N-Input NAND Gate
❖ Our V th expression for an N-input NAND gate becomes:

❖ The rule of thumb for an ideal symmetric equivalent inverter becomes:

CMOS 2-Input NAND Gate Layout
Complex CMOS Logic Circuits
Full-CMOS implementation of the XOR Gate function
 Complex CMOS Logic Circuits

❖ An example of the NMOS pull-down network synthesis is:

❖ D+E is created with two NMOS’s in parallel

❖ A(D+E) puts an NMOS in series with the (D+E) network
❖ The entire A(D+E) network is in parallel with the BC network
❖ The BC network is created with two series NMOS’s
 Complex CMOS Logic Circuits
❖ Complex CMOS Logic Graphs

❖ The complementary PMOS network is created with a technique called a dual pull-
up/down graph

❖ A graphical way to create the PMOS network for a given NMOS pull-down circuit.

❖ First create the pull-down graph by representing:

1) each NMOS transistor as an edge (i.e., a line), and

2) each node as a vertex (i.e., a dot)

- Orient the pull-down graph in the same orientation as the NMOS

circuit (Vout on top, VSS on bottom)
 Complex CMOS Logic Circuits
• Complex CMOS Logic Graphs

- Next, create the dual pull-up graph on top of the pull-down graph.

- Orient the pull-up graph with VDD on the left and Vout on the right.

- Create the pull-up graph using the rules:

1) a new vertex is created within each confined area of the pull-down graph
2) each vertex is connected by an edge which crosses each edge of the pull-down
graph

Fig: Construction of the dual pull-up graph from the pull-down graph, using the dual graph concept.
 Complex CMOS Logic Circuits
• Complex CMOS Logic Graphs

❖ We can now separate the graphs and synthesize the PMOS pull-up network
an edge (a line) = a transistor
Remember that:
a vertex (a dot) = a node
 Complex CMOS Logic Circuits

❖ Above figure shows the simple construction of the dual p-net (pull-up) graph from
the n-net (pull-down) graph.
❖ Each driver transistor in the pull-down network is represented by an edge, and each
node is represented by a vertex in the pull-down graph.
❖ Next, a new vertex is created within each confined area in the pull-down graph, and
neighboring vertices are connected by edges which cross each edge in the pull-down
graph only once.
❖ This new graph represents the pull-up network. The resulting CMOS complex logic
gate is shown in Fig.
 Layout of Complex CMOS Logic Gates

❖ Objective: To construct a minimum-area layout for the complex CMOS

logic gate. The stick-diagram layout is a "first attempt," using an arbitrary
ordering of the polysilicon gate columns.
❖ The separation between the polysilicon columns must allow for one
diffusion-to diffusion separation and two metal-to-diffusion contacts in
between. This certainly consumes a considerable amount of extra silicon
area.
❖ Thus to minimize the number of diffusion-area breaks for nMOS and for
pMOS transistors, the separation between the polysilicon gate columns
can be made smaller, which will reduce the overall horizontal dimension
and, hence, the circuit layout area. The number of diffusion breaks can be
minimized by changing the ordering of the polysilicon columns.
 Stick-diagram Layout of Complex
CMOS Logic Gates

Stick-diagram layout of the complex CMOS logic gate, with an arbitrary ordering of the polysilicon gate columns.
 Layout of Complex CMOS Logic Gates
Euler Path

❖ A simple method for finding the optimum gate ordering is the Euler-
path approach:
❖ find a Euler path in the pull-down graph and a Euler path in the
pull-up graph with identical ordering of input labels, i.e., find a
common Euler path for both graphs. The Euler path is defined as
an uninterrupted path that traverses each edge (branch) of the
graph exactly once.
 Euler Path

Figure: Finding a common Euler path in both graphs for n-net and p-net provides a gate
ordering that minimizes the number of diffusion breaks and, thus, minimizes the logic- gate
layout area. In both cases, the Euler path starts at (x) and ends at (y).
Euler Path
 Euler Path

❖ It is seen that there is a common sequence (E - D - A - B - C) in both

graphs, i.e., a 'Euler path’. The polysilicon gate columns can be arranged
according to this sequence, which results in uninterrupted p-type and n-
type diffusion areas.
❖ In the stick diagram of the new layout shown, the polysilicon column
separation d has to allow for only one metal-to-diffusion contact.
Advantages: more compact (smaller) layout area, simple routing of
signals, and consequently, less parasitic capacitance.
 Complex CMOS Logic Circuits

AOI / OAI CMOS Logic

❖ We classify the common types of logic expression forms as:

AOI AND-OR-INVERT

- A Sum-of-Products logic expression form:

F = A B + B'C + C' D

OAI -OR-AND-INVERT

- A Products-of-Sums logic expression form:

F = (A + B)(B'+C)(C'+D)

❖ We have the Invert portion in these forms so that we can directly synthesize the
NMOS pull-down network.
 Complex CMOS Logic Circuits
AOI / OAI CMOS Logic

AOI
 Complex CMOS Logic Circuits

AOI / OAI CMOS Logic

OAI
CMOS Full-Adder Circuit
CMOS Full-Adder Circuit
Example
Example
The Boolean function realized by this circuit is
The equivalent (WIL) ratios of the nMOS network and the pMOS network are
determined by using the series-parallel equivalency rules:
 Complex CMOS Logic Circuits
❖ Transmission Gate (Pass Gate)
❖ A Transmission Gate (T-gate or TG or pass gate) is a bi-directional switch made up
of an NMOS and PMOS is parallel.
❖ a control signal is connected to the gate of the NMOS (C) and its complement is
sent to the gate of the PMOS (C’)
❖ The T-gate is a bidirectional switch between A and B which is controlled by C
 Complex CMOS Logic Circuits
❖ Transmission Gate (Pass Gate)

❖ When the control signal C is HIGH :

(VDD)

Both transistors are turned on

A low resistance path exists between A and B

- When the control signal is LOW (0 V)

Both transistors are off
The T-gate looks like an open circuit

❖ This type of operation is commonly used in bus situations where only one gate can
drive the bus line at the same time
❖ T-gates are put on the output of each gate on the bus. The circuit that drives will use a T-
gate to connect to the bus with a low impedance path. All other circuits that aren’t driving
will switch their T-gates to be a high-impedance.
 Complex CMOS Logic Circuits

❖ Transmission Gate (Pass Gate)

❖ When the T-gate is on, the regions of operation of the transistors will depend
on Vin and Vout

❖ let’s say we drive Vin=VDD and initially Vout = 0 V

❖ As Vout moves from 0V to VDD, the regions of operation for the transistors
are as follows:

Bias conditions and operating regions of the CMOS transmission gate as function of the output voltage
Transmission Gate (Pass Gate)
 Transmission Gate (Pass Gate)
Total current flowing through the transmission gate is the sum of the NMOS drain current
and the PMOS drain current.
 Transmission Gate (Pass Gate)
Region 1:
 Transmission Gate (Pass Gate)
Region 2:
 Transmission Gate (Pass Gate)
Region 3:
 Transmission Gate (Pass Gate)

Equivalent resistance of the CMOS transmission gate plotted as a function of the output voltage
 Transmission Gate (Pass Gate)

Resistor equivalent Circuit

Transmission Gate (Pass Gate) Applications

XOR gate using Six Transistor

CMOS Transmission gates

XOR gate using Eight Transistor

CMOS Transmission gates
 Transmission Gate (Pass Gate) Applications

Two Input Multiplexer using

Two CMOS Transmission gates

Three variable Boolean function using

CMOS Transmission gates