128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

Document Title
4Bank x 2M x 16bits Synchronous DRAM

Revision History

Revision No. History Draft Date Remark

0.1 Initial Draft Jul. 2009 Preliminary

1.0 Release Aug. 2009

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Aug. 2009 1
 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

H57V1262GTRDESCRIPTION
The Hynix H57V1262GTR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. H57V1262GTR series is organized as 4banks of 2,097,152 x 16.

H57V1262GTR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)

FEATURES

• Voltage: VDD, VDDQ 3.3V supply voltage • Programmable Burst Length and Burst Type

• All device pins are compatible with LVTTL interface - 1, 2, 4, 8 or full page for Sequential Burst

• 54 Pin TSOPII (Lead Free Package) - 1, 2, 4 or 8 for Interleave Burst

• All inputs and outputs referenced to positive edge of • Programmable CAS Latency; 2, 3 Clocks
system clock
• Burst Read Single Write operation
• Data mask function by UDQM, LDQM
• Operating Temperature
• Internal four banks operation
- Commercial Temperature (0oC to 70oC)
• Auto refresh and self refresh
- Industrial Temperature (-40oC to 85oC)
• 4096 Refresh cycles / 64ms

● This product is in compliance with the directive pertaining of RoHS.

ORDERING INFORMATION
Part No. Clock Frequency Organization Interface Package
H57V1262GTR-50X 200MHz
H57V1262GTR-60X 166MHz
4Banks x 2Mbits x16 LVTTL 54 Pin TSOPII
H57V1262GTR-70X 143MHz
H57V1262GTR-75X 133MHz

Note:
1. H57V1262GTR-XXC Series: Normal power, Commercial Temp.(0oC to 70oC)
2. H57V1262GTR-XXI Series: Normal power, Industrial Temp. (-40oC to 85oC)
3. H57V1262GTR-XXL Series: Low power, Commercial Temp.(0oC to 70oC)
4. H57V1262GTR-XXJ Series: Low power, Industrial Temp. (-40oC to 85oC)

Rev. 1.0 / Aug. 2009 2

 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

PIN ASSIGNMENTS

VDD 1 54 VSS
DQ0 2 53 DQ15
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VSSQ 6 49 VDDQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VDDQ 9 46 VSSQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VSSQ 12 54 Pin TSOPII 43 VDDQ
DQ7 13 400mil x 875mil 42 DQ8
VDD 14 0.8mm pin pitch 41 VSS
LDQM 15 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS

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 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

PIN DESCRIPTION

SYMBOL TYPE DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM
CLK Clock
on the rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will
CKE Clock Enable
be one of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE, UDQM and LDQM

Selects bank to be activated during RAS activity

BA0, BA1 Bank Address
Selects bank to be read/written during CAS activity

Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8

A0 ~ A11 Address
Auto-precharge flag: A10

Row Address Strobe,

RAS, CAS and WE define the operation
RAS, CAS, WE Column Address Strobe,
Refer function truth table for details
Write Enable

Controls output buffers in read mode and masks input data in write
UDQM, LDQM Data Input/Output Mask
mode

DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin

VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

Rev. 1.0 / Aug. 2009 4

 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

FUNCTIONAL BLOCK DIAGRAM

2Mbit x 4banks x 16 I/O Synchronous DRAM

Self refresh Internal Row

logic & timer Counter

2Mx16 BANK 3
CLK
2Mx16 BANK 2
Row
Row Active Pre 2Mx16 BANK 1
CKE
Decoder X-Decoder 2Mx16 BANK 0
X-Decoder
State Machine

CS
X-Decoder DQ0

Sense AMP & I/O Gate

X-Decoder

I/O Buffer & Logic

RAS Refresh Memory
Cell
CAS Column Array
Active
WE Column
Pre
U/LDQM Decoder DQ15
Y-Decoder

Column Add
Bank Select Counter

A0 Address
Register
A1 Burst
Address Buffers

Counter

Pipe Line
A11 Control
CAS Latency
Mode Register Data Out Control
BA1
BA0

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 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

BASIC FUNCTIONAL DESCRIPTION

Mode Register

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 OP Code 0 0 CAS Latency BT Burst Length

OP Code

A9 Write Mode
Burst Type
0 Burst Read and Burst Write
1 Burst Read and Single Write A3 Burst Type
0 Sequential
1 Interleave

CAS Latency

A6 A5 A4 CAS Latency
Burst Length
0 0 0 Reserved
0 0 1 Reserved Burst Length
A2 A1 A0
0 1 0 2 A3 = 0 A3=1
0 1 1 3 0 0 0 1 1
1 0 0 Reserved 0 0 1 2 2
1 0 1 Reserved 0 1 0 4 4
1 1 0 Reserved 0 1 1 8 8
1 1 1 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved

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 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

ABSOLUTE MAXIMUM RATING

Parameter Symbol Rating Unit
Commercial Temperature 0 ~ 70
Ambient Temperature TA o
C
Industrial Temperature -40 ~ 85

Storage Temperature TSTG -55 ~ 125 o

C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD 1 W

Soldering Temperature / Time TSOLDER 260 / 10 oC

/ Sec

DC OPERATING CONDITION (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC)

Parameter Symbol Min. Typ Max Unit Note
Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1
Input High Voltage VIH 2.0 3.0 VDDQ + 0.3 V 1, 2
Input Low Voltage VIL -0.3 - 0.8 V 1, 3

Note:
1. All voltages are referenced to VSS = 0V
2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration

AC OPERATING TEST CONDITION

(Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC, VDD=3.3±0.3V, VSS=0V)

Parameter Symbol Value Unit Note

AC Input High / Low Level Voltage VIH / VIL 2.4 / 0.4 V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voltage Voutref 1.4 V
Output Load Capacitance for Access Time Measurement CL 50 pF

Vtt = 1.4V Vtt = 1.4V

RT = 500 Ω RT = 50Ω

Output Output Z0 = 50Ω

50pF 50pF

DC Output Load Circuit AC Output Load Circuit

Rev. 1.0 / Aug. 2009 7

 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

CAPACITANCE (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC, f=1MHz, VDD=3.3V)

Parameter Pin Symbol Min Max Unit

CLK CI1 2.0 4.0 pF

Input capacitance A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE,
CI2 2.5 5.0 pF
LDQM, UDQM

Data input / output capacitance DQ0 ~ DQ15 CI/O 3.0 5.5 pF

DC CHARACTERISTICS I (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC)

Parameter Symbol Min Max Unit Note

Input Leakage Current ILI -1 1 uA 1

Output Leakage Current ILO -1 1 uA 2

Output High Voltage VOH 2.4 - V IOH = -2mA

Output Low Voltage VOL - 0.4 V IOL = +2mA

Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 3.6

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 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

DC CHARACTERISTICS II (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC)

Speed (MHz)
Parameter Symbol Test Condition Unit Note
200 166 143 133

Burst length=1, One bank active

Operating Current IDD1 100 80 70 70 mA 1
tRC ≥ tRC(min), IOL=0mA

Precharge Standby Current IDD2P CKE ≤ VIL(max), tCK = 15ns 2 mA

in Power Down Mode IDD2PS CKE ≤ VIL(max), tCK = ∞ 2 mA

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns
Precharge Standby IDD2N Input signals are changed one time dur- 18
Current in Non Power ing 2clks. mA
Down Mode All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

IDD2NS 15
Input signals are stable.

Active Standby Current IDD3P CKE ≤ VIL(max), tCK = 15ns 5

mA
in Power Down Mode IDD3PS CKE ≤ VIL(max), tCK = ∞ 5

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns
IDD3N Input signals are changed one time dur- 40
Active Standby Current ing 2clks. mA
in Non Power Down Mode All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

IDD3NS 35
Input signals are stable.

Burst Mode Operating Cur- tCK ≥ tCK(min), IOL=0mA

IDD4 120 100 100 100 mA 1
rent All banks active

Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 210 200 190 190 mA 2

Normal 2 mA
Self Refresh Current IDD6 CKE ≤ 0.2V 3
Low power 800 uA

Note:
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. H57V1262GTR-XXC Series: Normal Power
H57V1262GTR-XXL Series: Low Power

Rev. 1.0 / Aug. 2009 9

 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

200 166 143 133
Speed
Parameter Unit Note
(MHz)
Min Max Min Max Min Max Min Max

CL = 3 tCK3 5.0 6.0 7.0 7.5 ns

100
System Clock Cycle Time 1000 1000 1000
0
CL = 2 tCK2 - - - 10 ns

Clock High Pulse Width tCHW 1.75 - 2.0 - 2.0 - 2.5 - ns 1

Clock Low Pulse Width tCLW 1.75 - 2.0 - 2.0 - 2.5 - ns 1

CL = 3 tAC3 - 4.5 - 5.4 - 5.4 - 5.4 ns

Access Time From Clock 2
CL = 2 tAC2 - - - - - - - 6.0 ns

Data-out Hold Time tOH 2.0 - 2.0 - 2.5 - 2.7 - ns

Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

Address Setup Time tAS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

Address Hold Time tAH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

Command Setup Time tCS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

Command Hold Time tCH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.0 - 1.5 - 1.5 - ns

CL = 3 tOHZ3 - 4.5 - 5.4 - 5.4 - 5.4 ns

CLK to Data Output in
High-Z Time
CL = 2 tOHZ2 - - - - - - - 6.0 ns

Note:
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to
the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 2.0V. If tR > 1ns, then (tR/2-0.5)ns
should be added to the parameter.

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 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

200 166 143 133
Speed
Parameter Unit Note
(MHz)
Min Max Min Max Min Max Min Max

RAS Cycle Time Operation tRC 55 - 60 - 63 - 63 - ns

Auto
RAS Cycle Time tRRC 55 - 60 - 63 - 63 - ns
Refresh

RAS to CAS Delay tRCD 15 - 18 - 20 - 20 - ns

120
RAS Active Time tRAS 38.7 100K 42 100K 42 100K 42 ns
K

RAS Precharge Time tRP 15 - 18 - 20 - 20 - ns

RAS to RAS Bank Active Delay tRRD 10 - 12 - 14 - 15 - ns

CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - CLK

Write Command to
tWTL 0 - 0 - 0 - 0 - CLK
Data-In Delay

Data-in to Precharge Command tDPL 2 - 2 - 2 - 2 - CLK

Data-In to Active Command tDAL tDPL + tRP

DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - CLK

DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - CLK

MRS to New Command tMRD 2 - 2 - 2 - 2 - CLK

CL = 3 tPROZ3 3 - 3 - 3 - 3 - CLK
Precharge to
Data Output High-Z
CL = 2 tPROZ2 - - - - - - 2 - CLK

Power Down Exit Time tDPE 1 - 1 - 1 - 1 - CLK

Self Refresh Exit Time tSRE 1 - 1 - 1 - 1 - CLK 1

Refresh Time tREF - 64 - 64 - 64 - 64 ms

Note:
1. A new command can be given tRRC after self refresh exit.

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 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

COMMAND TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA Note

Mode Register Set H X L L L L X OP code

H X X X
No Operation H X X X
L H H H

Bank Active H X L L H H X RA V

Read L
H X L H L H X CA V
Read with Autopre-
H
charge

Write L
H X L H L L X CA V
Write with Autopre-
H
charge

Precharge All Banks H X

H X L L H L X X
Precharge selected Bank L V

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

Burst-Read-Single- A9 ball High MRS

H X L L L L X
WRITE (Other balls OP code) Mode

Entry H L L L L H X

Self Refresh H X X X X
Exit L H X
L H H H

H X X X
Entry H L X
L H H H
Precharge
X
power down
H X X X
Exit L H X
L H H H

H X X X
Entry H L X
Clock Suspend L V V V X

Exit L H X X

Rev. 1.0 / Aug. 2009 12

 Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series

PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package

UNIT : mm(inch)

11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720) 10.262(0.4040)
10.058(0.3960)

0.150(0.0059) 1.194(0.0470)
0.050(0.0020) 0.991(0.0390)

0.400(0.016) 5deg 0.597(0.0235) 0.210(0.0083)

0.80(0.0315)BSC 0deg 0.406(0.0160) 0.120(0.0047)
0.300(0.012)

Rev. 1.0 / Aug. 2009 13