DIGITAL CIRCUITS

M I N I P ROJ EC T 1

MADE BY:CO24BTECH11012
 CIRCUIT
DIAGRAM FOR
ALL THE
MODULES
NAND GATE

• module nand_gate(
• input a,b,
• output y
• );
• nand #1 (y, a, b);
• endmodule
OR GATE

• module or_gate(
• input a,b,
• output y
• );
• or #1 (y, a, b);
• endmodule
XOR GATE
• module xor_gate(
• input a,b,
• output y
• );
• wire [2:0] y1;

• nand_gate uut(.a(a), .b(b), .y(y1[2]));

• nand_gate dut(.a(a), .b(y1[2]), .y(y1[1]));
• nand_gate fut(.a(y1[2]), .b(b), .y(y1[0]));
• nand_gate ut(.a(y1[0]), .b(y1[1]), .y(y));
• endmodule
HALF ADDER

• module half_adder(
• input a,b,
• output [1:0] y
• );
• wire carry;
•
nand_gate uut(.a(a), .b(b), .y(carry));
• xor_gate sum_gate(.a(a), .b(b), .y(y[0]));
• nand_gate not_carry(.a(carry), .b(carry), .y(y[1]));
• endmodule
FULL ADDER
• module full_adder(
• input a,b,ck_1,
• output sum,
• output carry_out
• );
• wire [1:0] y;
• wire [1:0] result;
•
half_adder first_sum(.a(a), .b(b), .y(y));
• half_adder second_sum(.a(y[0]), .b(ck_1), .y(result));
•
assign sum = result[0];
• or_gate carry(.a(y[1]), .b(result[1]), .y(carry_out));
• endmodule
RIPPLE CARRY ADDER 4-BIT
• input [3:0] a,b,
• output [3:0] sum,
• output overflow
• );
• wire [2:0] carry;
• wire carry_out_of_last_fa;
• reg carry0=0;
• full_adder fa0(.a(a[0]), .b(b[0]), .ck_1(carry0), .sum(sum[0]), .carry_out(carry[0]));
• full_adder fa1(.a(a[1]), .b(b[1]), .ck_1(carry[0]), .sum(sum[1]), .carry_out(carry[1]));
• full_adder fa2(.a(a[2]), .b(b[2]), .ck_1(carry[1]), .sum(sum[2]), .carry_out(carry[2]));
• full_adder fa3(.a(a[3]), .b(b[3]), .ck_1(carry[2]), .sum(sum[3]), .carry_out(carry_out_of_last_fa));
• xor_gate overflow_logic(
• .a(carry_out_of_last_fa),.b(carry[2]),.y(overflow)
);endmodule
 TIME DELAY
CALCULATIONS
 TIME DELAY FOR MODULES (NAND & XOR GATE)

• 1. NAND Gate
• The NAND gate is the basic building block used in constructing other gates (XOR, OR).
• Given: Delay for each NAND gate = 1 ns.
• 2. XOR Gate
• The XOR gate is used to compute the sum in both the half adder and full adder.
• The XOR gate is constructed using four NAND gates.
• Total delay of XOR gate: Each XOR gate consists of 2 NAND gates in parallel and their
combination in series with 2 more NAND gates.
• Delay for XOR = 3×1 ns=3 ns.
TIME DELAY FOR MODULES (OR GATE & HALF ADDER)

• 3. OR Gate
• The OR gate is used to compute the carry output in the full adder.
• The OR gate is constructed using three NAND gates with 2 in parallel and one in series.
• Total delay of OR gate: 2×1 ns=2 ns.
• 4.Half Adder Delay
• The half adder consists of one XOR gate (for sum) and one NAND gate (for carry).
• Sum output (Half Adder):
• Delay = delay of one XOR gate = 3ns.
• Carry output (Half Adder):
• Delay = delay of two NAND gate = 2 ns.
• Total delay of Half Adder:
• Maximum delay between sum and carry: max(3 ns,2 ns)=3
 TIME DELAY FOR MODULES (FULL ADDER)
• Sum output (Full Adder):
• Full Adder Delay
• Sum delay = delay through both XOR gates (one from
• The full adder consists of two half adders and one each half adder).
OR gate for carry propagation.
• Sum delay = 3 ns+3 ns=6 ns.
1. First Half Adder:
• Carry output (Full Adder):
1. Sum delay: 3ns (due to XOR gate).
• The carry-out is determined by the maximum of the carry
2. Carry delay: 1 ns (due to NAND gate). delays and the OR gate delay.

2. Second Half Adder:. • Carry delay = 1 ns+2 ns=3 ns.

1. Sum delay: 3 ns (due to XOR gate). • Total delay of Full Adder:

2. Carry delay: 1 ns (due to NAND gate). • Maximum delay between sum and carry:
max(6 ns,3 ns)=6 ns.
3. Carry-out (Full Adder):
1. The OR gate combines the carry outputs from
both half adders.
2. OR gate delay = 2 ns.
TIME DELAY FOR MODULES (RIPPLE CARRY ADDER 4 BIT)

• Ripple Carry Adder Delay

• The ripple carry adder consists of four full adders connected in series. The delay is calculated
by considering the worst-case scenario where the carry propagates through all full adders.
• Each full adder has a time delay of 6 ns . In total for 4 bits , 4 full adders are used . Hence the
time delay is given by :
• Total delay = 4*(Delay of each full adder)
• Total delay= 4*(6)=24 ns
 TOTAL TIME DELAY

• The total time delay is given by the sum of time delay of the ripple carry adder and the
overflow logic
• Time delay for overflow logic = time delay of one XOR gate = 3 ns
• Time delay for ripple carry adder = 24 ns

• TOTAL TIME DELAY = 24 + 3=27 ns

DESIGN CODE
• USED Signed bit system(2’s complement) • module xor_gate(

• module nand_gate( • input a,b,

• input a,b, • output y

• );
• output y
• wire [2:0] y1;
• );
• nand_gate uut(.a(a), .b(b), .y(y1[2]));
• nand #1 (y, a, b);
• nand_gate dut(.a(a), .b(y1[2]), .y(y1[1]));
• endmodule
• nand_gate fut(.a(y1[2]), .b(b), .y(y1[0]));
• module or_gate(
• nand_gate ut(.a(y1[0]), .b(y1[1]), .y(y));
• input a,b, • endmodule
• output y • module half_adder(
• ); • input a,b,
• wire [1:0] y2; • output [1:0] y
• nand_gate uut(.a(a), .b(a), .y(y2[1])); • );

• nand_gate dut(.a(b), .b(b), .y(y2[0])); • wire carry;

nand_gate uut(.a(a), .b(b), .y(carry));
• nand_gate dsut(.a(y2[1]), .b(y2[0]), .y(y));
• xor_gate sum_gate(.a(a), .b(b), .y(y[0]));
• endmodule • nand_gate not_carry(.a(carry), .b(carry),
.y(y[1]));
• endmodule
 • module ripple_carry_adder(
• module full_adder(
• input [3:0] a,b,
• input a,b,ck_1, • output [3:0] sum,
• output sum, • output overflow
• );
• output carry_out
• wire [2:0] carry;
• ); • wire carry_out_of_last_fa;

• wire [1:0] y; • reg carry0=0;

• full_adder fa0(.a(a[0]), .b(b[0]), .ck_1(carry0),
• wire [1:0] result; .sum(sum[0]), .carry_out(carry[0]));
• full_adder fa1(.a(a[1]), .b(b[1]), .ck_1(carry[0]),
• .sum(sum[1]), .carry_out(carry[1]));
half_adder first_sum(.a(a), .b(b), .y(y)); • full_adder fa2(.a(a[2]), .b(b[2]), .ck_1(carry[1]),
.sum(sum[2]), .carry_out(carry[2]));
• half_adder second_sum(.a(y[0]), .b(ck_1),
• full_adder fa3(.a(a[3]), .b(b[3]), .ck_1(carry[2]),
.y(result)); .sum(sum[3]), .carry_out(carry_out_of_last_fa));

• • xor_gate overflow_logic(

assign sum = result[0]; • .a(carry_out_of_last_fa),.b(carry[2]),.y(overflow)

);endmodule
• or_gate carry(.a(y[1]), .b(result[1]),
.y(carry_out));
• endmodule
TEST BENCH CODE
• `timescale 1ns/100ps • // Test Case 1: Add 4'b0000 + 4'b0000
• `include "ripplecarryadder.v“ • a = 4'b0000; b = 4'b0000; #20;
• // Test Case 2: Add 4'b0001 + 4'b0001
module ripple_carry_adder_tb; • a = 4'b0001; b = 4'b0001; #20;
• reg [3:0] a, b; // Test Case 3: Add 4'b1111 + 4'b0001
• wire [3:0] sum; • a = 4'b1111; b = 4'b0001; #20;
• wire overflow; // Test Case 4: Add 4'b1001 + 4'b0111

• ripple_carry_adder uut ( • a = 4'b1001; b = 4'b0111; #20;

// Test Case 5: Add 4'b0101 + 4'b0101
• .a(a),
• a = 4'b0101; b = 4'b0101; #20;
• .b(b),
// Test Case 6: Add 4'b0011 + 4'b1101
• .sum(sum),
• a = 4'b0011; b = 4'b1101; #20;
• .overflow(overflow)
// Test Case 7: Add 4'b0110 + 4'b0010
• );
• a = 4'b0110; b = 4'b0010; #20;
• initial begin
//Test Case 8: Add 4'b0010 + 4'b0011
• $dumpfile("ripplecarryadder.vcd");
• a = 4'b0010; b = 4'b0011; #20;
• $dumpvars(0,ripple_carry_adder_tb);
•
// Test Case 9: Add 4'b0100 + 4'b0100
• a = 4'b0100; b = 4'b0100; #20;
//Test Case 10: Add 4'b1100 + 4'b0010
• a = 4'b1100; b = 4'b0010; #20;
//Test Case 11: Add 4'b0111 + 4'b0111
• a = 4'b0111; b = 4'b0111; #20;
//Test Case 12: Add 4'b1110 + 4'b0001
• a = 4'b1110; b = 4'b0001; #20;
• $finish;
• end
•
always@(*) begin
• $monitor("Time = %0t ns, a = %b, b = %b -> Sum = %b, Overflow = %b", $time, a,
b,sum, overflow);
• end
•
endmodule
SIMULATION RESULT
MONITOR RESULTS
WAVE FORMS