Department of Electrical Engineering
Faculty Member: Dr. Abdullah Mughees Dated: 8/10/24
Semester:_3rd Section: BEE-15D
Group No.:03
EE-221: Digital Logic Design
Lab 4: Design and Implementation of Simple Practical Circuits with Full Adder
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7
Name Reg. No Viva / Lab Analysis of Modern Ethics and Individual Total
Performanc data in Lab Tool Usage Safety and Team marks
e Report Work Obtained
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks
Kumail Ahmed 459196
Ali Shahzad 479722
Muhammad Ayyan Iqbal 465330
Mirza
M. Ahmed 462222
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Table of Contents
Lab Task 1: .................................................................................................................................................................. 2
Truth Table .............................................................................................................................................................. 2
Hardware Implementation: ......................................................................................................................................... 3
Proteus Simulation: ..................................................................................................................................................... 6
Lab Task 2: .................................................................................................................................................................. 7
WAVE FORM: .......................................................................................................................................................... 8
Lab Task 3: .................................................................................................................................................................. 9
CODE ....................................................................................................................................................................... 9
Observations/Comments:...........................................................................................................................................10
Lab Task 1: (5 Marks)
Implement the Full Adder Circuit given below, make its truth table and run the circuit on Proteus.
Truth Table
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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Hardware Implementation:
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Proteus Simulation:
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Lab Task 2: (3 Marks)
Simulate the gate-level model of the circuit you patched in task 1. Give the code and resulted waveform in
the space provided below.
module task1(S, Cout, A, B, Cin);
input A, B, Cin;
output S, Cout;
wire w1, w2, w3;
xor x1(w1, A, B);
xor x2(S, w1, Cin);
and a1(w2, A, B);
and a2(w3, w1, Cout);
or o1(Cout, w3, w2);
endmodule
module task1_kumail;
reg A, B, Cin;
wire S, Cout;
task1 t1(S, Cout, A, B, Cin);
initial
begin
#100 A = 1'b0; B = 1'b0; Cin = 1'b0;
#100 A = 1'b0; B = 1'b0; Cin = 1'b1;
#100 A = 1'b0; B = 1'b1; Cin = 1'b0;
#100 A = 1'b0; B = 1'b1; Cin = 1'b1;
#100 A = 1'b1; B = 1'b0; Cin = 1'b0;
#100 A = 1'b1; B = 1'b0; Cin = 1'b1;
#100 A = 1'b1; B = 1'b1; Cin = 1'b0;
#100 A = 1'b1; B = 1'b1; Cin = 1'b1;
end
endmodule
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WAVE FORM:
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Lab Task 3: (2 Marks)
CODE
Write Verilog code to implement full adder using two half adder circuits.
module full_adder(Sum, Cout, A, B, Cin);
input A, B, Cin;
wire w1, w2, w3;
output Sum, Cout;
half_adder h1(w1, w2, A, B);
half_adder h2(Sum, w3, w1, Cin);
or o1(Cout, w3, w2);
endmodule
module task3_kumail;
reg A, B, Cin;
wire SUM, Cout;
full_adder f1(SUM, Cout, A, B, Cin);
initial
begin
#100 A = 1'b0; B = 1'b0; Cin = 1'b0;
#100 A = 1'b0; B = 1'b0; Cin = 1'b1;
#100 A = 1'b0; B = 1'b1; Cin = 1'b0;
#100 A = 1'b0; B = 1'b1; Cin = 1'b1;
#100 A = 1'b1; B = 1'b0; Cin = 1'b0;
#100 A = 1'b1; B = 1'b0; Cin = 1'b1;
#100 A = 1'b1; B = 1'b1; Cin = 1'b0;
#100 A = 1'b1; B = 1'b1; Cin = 1'b1;
end
endmodule
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Observations/Comments:
Observations:
In this lab, a Full Adder circuit was successfully implemented and verified through its truth
table. The logic gates were connected as per the design, and the circuit was simulated using
Proteus software. The simulation confirmed the correct operation of the Full Adder,
producing the expected sum and carry outputs for all possible input combinations. The
Verilog code for the Full Adder using two Half Adders was also implemented and
synthesized. The gate-level simulation produced waveforms that matched the theoretical
truth table, validating the design.
Comments:
The implementation of the Full Adder circuit was straightforward, with the truth table
serving as an effective reference to verify the results. The gate-level simulation in Proteus
and the Verilog coding exercise highlighted how complex logic functions can be modularly
designed using smaller building blocks like Half Adders. The lab provided a practical
understanding of digital circuit design and HDL (Hardware Description Language)
implementation techniques.
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