LTC6990

TimerBlox: Voltage Controlled

Silicon Oscillator
FEATURES DESCRIPTION
n Fixed-Frequency or Voltage-Controlled Operation The LTC®6990 is a precision silicon oscillator with a pro-
n Fixed: Single Resistor Programs Frequency with grammable frequency range of 488Hz to 2MHz. It can be
<1.5% Max Error used as a fixed-frequency or voltage-controlled oscillator
n VCO: Two Resistors Set VCO Center Frequency (VCO). The LTC6990 is part of the TimerBlox® family of
and Tuning Range versatile silicon timing devices.
n Frequency Range: 488Hz to 2MHz
A single resistor, RSET, programs the LTC6990’s inter-
n 2.25V to 5.5V Single Supply Operation
nal master oscillator frequency. The output frequency
n 72µA Supply Current at 100kHz
is determined by this master oscillator and an internal
n 500µs Start-Up Time
frequency divider, NDIV, programmable to eight settings
n VCO Bandwidth >300kHz at 1MHz
from 1 to 128.
n CMOS Logic Output Sources/Sinks 20mA
n 50% Duty Cycle Square Wave Output 1MHz 50kΩ
fOUT = • , NDIV = 1, 2, 4 …128
n Output Enable (Selectable Low or Hi-Z When Disabled) NDIV R SET
n 55°C to 125°C Operating Temperature Range
n Available in Low Profile (1mm) SOT-23 (ThinSOT™) Optionally, a second resistor at the SET input provides
and 2mm × 3mm DFN Package linear voltage control of the output frequency and can be
n AEC-Q100 Qualified for Automotive Applications used for frequency modulation. A narrow or wide VCO
tuning range can be configured by the appropriate selec-
tion of the two resistors.
APPLICATIONS The LTC6990 includes an enable function that is synchro-
n Low Cost Precision Programmable Oscillator
nized with the master oscillator to ensure clean, glitch-
n Voltage-Controlled Oscillator
free output pulses. The disabled output can be configured
n High Vibration, High Acceleration Environments
to be high impedance or forced low.
n Replacement for Fixed Crystal and Ceramic Oscillators
n Portable and Battery-Powered Equipment For easy configuration of the LTC6990, use the TimerBlox
All registered trademarks and trademarks are the property of their respective owners. Protected LTC6990: Voltage Controlled Oscillator Web-Based
by U.S. patents, including 6342817, 6614313. Design Tool.

TYPICAL APPLICATION
Voltage Controlled Oscillator with 16:1 Frequency Range VCO Transfer Function
1000

MHz
V+ fOUT = 2MHz − VCTRL •
V
750
OE OUT
fOUT (kHz)

LTC6990 V+
500
GND V+
RVCO C1
100k 0.1µF
250
VCTRL SET DIV
RSET 6990 TA01a

100k
0
0 0.5 1 1.5 2
VCTRL (V)
6990 TA01b

Rev. D

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LTC6990
ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage (V+) to GND.........................................6V Specified Temperature Range (Note 3)

Maximum Voltage on Any Pin LTC6990C................................................. 0°C to 70°C
.............................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V) LTC6990I..............................................–40°C to 85°C
Operating Temperature Range (Note 2) LTC6990H........................................... –40°C to 125°C
LTC6990C.............................................–40°C to 85°C LTC6990MP........................................ –55°C to 125°C
LTC6990I..............................................–40°C to 85°C Junction Temperature............................................ 150°C
LTC6990H........................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C
LTC6990MP........................................ –55°C to 125°C Lead Temperature (Soldering, 10sec).................... 300°C

PIN CONFIGURATION
TOP VIEW
TOP VIEW
V+ 1 6 OUT
OE 1 6 OUT
DIV 2 7 5 GND
GND 2 5 V+
SET 3 4 OE
SET 3 4 DIV

DCB PACKAGE S6 PACKAGE

6-LEAD (2mm × 3mm) PLASTIC DFN 6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL

ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6990CDCB#TRMPBF LTC6990CDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6990IDCB#TRMPBF LTC6990IDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6990HDCB#TRMPBF LTC6990HDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LTC6990CS6#TRMPBF LTC6990CS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6990IS6#TRMPBF LTC6990IS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6990HS6#TRMPBF LTC6990HS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6990MPS6#TRMPBF LTC6990MPS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –55°C to 125°C
AUTOMOTIVE PRODUCTS**
LTC6990IS6#WTRMPBF LTC6990IS6#WTRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6990HS6#WTRMPBF LTC6990HS6#WTRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.

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 LTC6990
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15
(NDIV = 1 to 128), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fOUT Output Frequency Recommended Range: RSET = 50k to 800k 0.488 1000 kHz
Extended Range: RSET = 25k to 800k 0.488 2000 kHz
∆fOUT Frequency Accuracy (Note 4) Recommended Range ±0.8 ±1.5 %
RSET = 50k to 800k l ±2.2 %
Extended Range ±2.4 %
RSET = 25k to 800k l ±3.2 %
∆fOUT/∆T Frequency Drift Over Temperature l ±0.005 %/°C
∆fOUT/∆V+ Frequency Drift Over Supply V+ = 4.5V to 5.5V l 0.23 0.55 %/V
V+ = 2.25V to 4.5V l 0.06 0.16 %/V
Long-Term Frequency Stability (Note 11) 90 ppm/√kHr
Period Jitter (Note 10) NDIV = 1 0.38 %P-P
NDIV = 2 0.22 %P-P
0.027 %RMS
NDIV = 128 0.022 %P-P
0.004 %RMS
Duty Cycle NDIV = 1, RSET = 25k to 800k l 47 50 53 %
NDIV > 1, RSET = 25k to 800k l 48 50 52 %
BW Frequency Modulation Bandwidth 0.4•fOUT kHz
tS Frequency Change Settling Time tMASTER = tOUT /NDIV 6•tMASTER µs
(Note 9)
Analog Inputs
VSET Voltage at SET Pin l 0.97 1.00 1.03 V
∆VSET /∆T VSET Drift Over Temperature l ±75 µV/°C
∆VSET /∆V+ VSET Drift Over Supply –150 µV/V
∆VSET /∆ISET VSET Droop with ISET –7 Ω
RSET Frequency-Setting Resistor Recommended Range l 50 800 kΩ
Extended Range l 25 800 kΩ
VDIV DIV Pin Voltage l 0 V+ V
∆VDIV /V+ DIV Pin Valid Code Range (Note 5) Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16 l ±1.5 %
DIV Pin Input Current l ±10 nA
Power Supply
V+ Operating Supply Voltage Range l 2.25 5.5 V
Power-On Reset Voltage RSET = 25k to 800k l 1.95 V
IS Supply Current RL = ∞, NDIV = 1, RSET = 50k V+ = 5.5V l 235 283 µA
V+ = 2.25V l 145 183 µA
RL = ∞, NDIV = 1 RSET = 800k V+ = 5.5V l 71 105 µA
V+ = 2.25V l 59 92 µA
RL = ∞, NDIV = 128, RSET = 50k V+ = 5.5V l 137 180 µA
V+ = 2.25V l 106 145 µA
RL = ∞, NDIV = 128, RSET = 800k V+ = 5.5V l 66 100 µA
V+ = 2.25V l 56 90 µA

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LTC6990
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15
(NDIV = 1 to 128), RSET = 25k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital I/O
OE Pin Input Capacitance 2.5 pF
OE Pin Input Current OE = 0V to V+ l ±10 nA
VIH High Level OE Pin Input Voltage (Note 6) l 0.7•V+ V
VIL Low Level OE Pin Input Voltage (Note 6) l 0.3•V+ V
OUT Pin Hi-Z Leakage OE = 0V, DIVCODE ≥ 8, OUT = 0V to V+ ±10 µA
IOUT(MAX) Maximum Output Current ±20 mA
VOH High Level Output Voltage V+ = 5.5V IOH = –1mA l 5.45 5.48 V
(Note 7) IOH = –16mA l 4.84 5.15 V
V+ = 3.3V IOH = –1mA l 3.24 3.27 V
IOH = –10mA l 2.75 2.99 V
V+ = 2.25V IOH = –1mA l 2.17 2.21 V
IOH = –8mA l 1.58 1.88 V
VOL Low Level Output Voltage V+ = 5.5V IOL = 1mA l 0.02 0.04 V
(Note 7) IOL = 16mA l 0.26 0.54 V
V+ = 3.3V IOL = 1mA l 0.03 0.05 V
IOL = 10mA l 0.22 0.46 V
V+ = 2.25V IOL = 1mA l 0.03 0.07 V
IOL = 8mA l 0.26 0.54 V
tPD Output Disable Propagation Delay V+ = 5.5V 17 ns
V+ = 3.3V 26 ns
V+ = 2.25V 44 ns
tENABLE Output Enable Time NDIV ≤ 2, tOUT = 1/fOUT tPD to tOUT µs
NDIV ≥ 4, tMASTER = tOUT/NDIV tPD to 2•tMASTER µs
tr Output Rise Time (Note 8) V+ = 5.5V 1.1 ns
V+ = 3.3V 1.7 ns
V+ = 2.25V 2.7 ns
tf Output Fall Time (Note 8) V+ = 5.5V 1.0 ns
V+ = 3.3V 1.6 ns
V+ = 2.25V 2.4 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
may cause permanent damage to the device. Exposure to any Absolute of how the DIV pin voltage selects the value of DIVCODE.
Maximum Rating condition for extended periods may affect device Note 6: The OE pin has hysteresis to accommodate slow rising or falling
reliability and lifetime. signals. The threshold voltages are proportional to V+. Typical values can
Note 2: The LTC6990C is guaranteed functional over the operating be estimated at any supply voltage using VOE(RISING) ≈ 0.55 • V+ + 185mV
temperature range of –40°C to 85°C. and VOE(FALLING) ≈ 0.48 • V+ – 155mV.
Note 3: The LTC6990C is guaranteed to meet specified performance from Note 7: To conform to the Logic IC Standard, current out of a pin is
0°C to 70°C. The LTC6990C is designed, characterized and expected to arbitrarily given a negative value.
meet specified performance from –40°C to 85°C but it is not tested or Note 8: Output rise and fall times are measured between the 10% and the
QA sampled at these temperatures. The LTC6990I is guaranteed to meet 90% power supply levels with 5pF output load. These specifications are
specified performance from –40°C to 85°C. The LTC6990H is guaranteed based on characterization.
to meet specified performance from –40°C to 125°C. The LTC6990MP is Note 9: Settling time is the amount of time required for the output to settle
guaranteed to meet specified performance from –55°C to 125°C. within ±1% of the final frequency after a 0.5x or 2x change in ISET.
Note 4: Frequency accuracy is defined as the deviation from the fOUT Note 10: Jitter is the ratio of the deviation of the period to the mean of the
equation, assuming RSET is used to program the frequency. period. This specification is based on characterization and is not 100% tested.

Rev. D

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 LTC6990
ELECTRICAL CHARACTERISTICS
Note 11: Long-term drift of silicon oscillators is primarily due to the the square root and multiply by the typical drift number. For instance, a
movement of ions and impurities within the silicon and is tested at 30°C year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift
under otherwise nominal operating conditions. Long-term drift is specified without power applied to the device may be approximated as 1/10th of the
as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate drift with power, or 9ppm/√kHr for a 90ppm/√kHr device.
drift for a set time period, translate that time into thousands of hours, take

TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3.3V, unless otherwise noted.

Frequency Error
Frequency Error vs RSET vs Supply Voltage Frequency Error vs Temperature
4 0.5 1.5
TA = 25°C TA = 25°C V+ = 3.3V
3 GUARANTEED MAX 0.4 DIVCODE = 4
OVER TEMPERATURE 1.0
0.3
2
FREQUENCY ERROR (%)
FREQUENCY ERROR (%)

0.2 RSET = 800k

0.5
1 TYPICAL MAX 0.1

ERROR (%)
RSET = 50k
0 90% OF UNITS 0 0.0
RSET = 200k RSET = 800k
–1 TYPICAL MIN –0.1
–0.5
–0.2 RSET = 50k
–2 RSET = 267k
GUARANTEED MIN –0.3
–1.0
–3 OVER TEMPERATURE –0.4
–4 –0.5 –1.5
10 100 1000 2 3 4 5 6 –50 –25 0 25 50 75 100 125
RSET (kΩ) SUPPLY VOLTAGE (V) TEMPERATURE (°C)
6990 G01 6990 G02 6990 G03

VSET vs ISET VSET vs Supply Voltage VSET vs Temperature

1.003 1.003 1.020
V+ = 3.3V RSET = 200k RSET = 200k
TA = 25°C TA = 25°C 1.015 3 TYPICAL PARTS

1.010
1.002 1.002
1.005
VSET (V)
VSET (V)
VSET (V)

1.000

0.995
1.001 1.001
0.990

0.985

1.000 1.000 0.980

0 10 20 30 40 2 3 4 5 6 –50 –25 0 25 50 75 100 125
ISET (µA) SUPPLY VOLTAGE (V) TEMPERATURE (°C)
6990 G04 6990 G05 6990 G06

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LTC6990
TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3V, unless otherwise noted.

Typical VSET Distribution Supply Current vs Supply Voltage Supply Current vs Temperature
300 250 250
TA = 25°C TA = 25°C
RSET = 50k, ÷1 5.5V, RSET = 50k, ÷1
2 LOTS
250 DFN AND SOT-23

POWER SUPPLY CURRENT (µA)

POWER SUPPLY CURRENT (µA)

200 RSET = 50k, ÷2 200
1416 UNITS
NUMBER OF UNITS

200
2.25V, RSET = 50k, ÷1
150 RSET = 50k, ÷128 150
150 5.5V, RSET = 50k, ÷128
100 100
100 5.5V, RSET = 800k, ÷1
RSET = 800k, ÷1
50 RSET = 800k, ÷128 50 2.25V, RSET = 800k, ÷128
50

0 0 0
0.986 0.994 1.002 1.010 1.018 2 3 4 5 6 –50 –25 0 25 50 75 100 125
VSET (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C)
6990 G07 6990 G05 6990 G09

Supply Current vs Frequency, 5V Supply Current vs Frequency, 2.5V Supply Current vs OE Pin Voltage
400 400 200
RECOMMENDED RANGE RECOMMENDED RANGE TA = 25°C
350 EXTENDED RANGE EXTENDED RANGE RSET = 800k
350 5V, OE RISING
175 DIVCODE = 7

POWER SUPPLY CURRENT (µA)

POWER SUPPLY CURRNET (µA)

POWER SUPPLY CURRNET (µA)

300 300
÷2 150 5V, OE FALLING
250 250 ÷1
3.3V, OE FALLING 3.3V,
200 200 ÷2 125 OE RISING

150 ÷128 150

÷1 100
÷128
100 100
75
50 V+ = 5V 50 V+ = 2.5V
TA = 25°C TA = 25°C
0 0 50
0.1 1 10 100 1000 10000 0.1 1 10 100 1000 10000 0 20 40 60 80 100
FREQUENCY (kHz) FREQUENCY (kHz) VOE /V+ (%)
6990 G10 6990 G11 6990 G12

OE Threshold Voltage Output Resistance

Peak-to-Peak Jitter vs Frequency vs Supply Voltage vs Supply Voltage
0.50 3.5 50
TA = 25°C TA = 25°C TA = 25°C
0.45 V+ = 5V 45
PEAK-TO-PEAK PERIOD 3.0
0.40 DEVIATION MEASURED ÷1 POSITIVE-GOING 40
OUTPUT RESISTANCE (Ω)

0.35 OVER 30sec INTERVALS 2.5 35

OE PIN VOLTAGE (V)

OUTPUT SOURCING CURRENT

JITTER (%P-P)

0.30 2.0 30
0.25 NEGATIVE-GOING 25
÷2 1.5
0.20 20
0.15 ÷4 1.0 15 OUTPUT SINKING CURRENT
0.10 10
0.5
0.05 ÷128 5
0 0 0
0.1 1 10 100 1000 2 3 4 5 6 2 3 4 5 6
FREQUENCY (kHz) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
6990 G13 6990 G14 6990 G15

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 LTC6990
TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3V, unless otherwise noted.

Typical Frequency Error vs Rise and Fall Time Output Disable Propagation Delay
Time (Long-Term Drift) vs Supply Voltage (tPD) vs Supply Voltage
200 3.0 50
65 UNITS TA = 25°C TA = 25°C
150 SOT-23 AND DFN PARTS CLOAD = 5pF 45 CLOAD = 5pF
TA = 30°C 2.5
40
100

PROPAGATION DELAY (ns)

DELTA FREQUENCY (ppm)

35

RISE/FALL TIME (ns)

2.0
50
tRISE 30
0 1.5 25
tFALL
–50 20
1.0
15
–100
10
0.5
–150
5
–200 0 0
0 400 800 1200 1600 2000 2400 2800 2 3 4 5 6 2 3 4 5 6
TIME (h) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
6990 G15a 6990 G16 6990 G17

Typical ISET Current Limit vs V+ Typical Output Waveform

1000
TA = 25°C V+ = 3.3V
SET PIN SHORTED TO GND DIVCODE = 2
RSET = 200k
800

600 OE
ISET (µA)

2V/DIV

400 OUT
2V/DIV

200

0 6990 G19
2 3 4 5 6 20µs/DIV
SUPPLY VOLTAGE (V)
6990 G18

Frequency Modulation Frequency Modulation

VCTRL VCTRL
2V/DIV 2V/DIV

OUT OUT
2V/DIV 2V/DIV

fOUT fOUT
50kHz/DIV 50kHz/DIV

6990 G20
20µs/DIV 20µs/DIV 6990 G21

V+ = 3.3V, DIVCODE = 0 V+ = 3.3V, DIVCODE = 0

RSET = 200k, RVCO = 464k RSET = 200k, RVCO = 464k
fOUT = 175kHz to 350kHz fOUT = 175kHz to 350kHz

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LTC6990
PIN FUNCTIONS (DCB/S6)

V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This Limit the capacitance on the SET pin to less than 10pF
supply must be kept free from noise and ripple. It should to minimize jitter and ensure stability. Capacitance less
be bypassed directly to the GND pin with a 0.1µF capacitor. than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
DIV (Pin 2/Pin 4): Programmable Divider and Hi-Z Mode
Input. A V+ referenced A/D converter monitors the DIV V+
pin voltage (VDIV) to determine a 4-bit result (DIVCODE).
VDIV may be generated by a resistor divider between V+
OE OUT
LTC6990 V+
and GND. Use 1% resistors to ensure an accurate result.
GND V+
The DIV pin and resistors should be shielded from the C1
0.1µF R1
OUT pin or any other traces that have fast edges. Limit
SET DIV
the capacitance on the DIV pin to less than 100pF so that
RSET 6990 PF
R2
VDIV settles quickly. The MSB of DIVCODE (Hi-Z) deter-
mines the behavior of the output when OE is driven low.
If Hi-Z = 0 the output is pulled low when disabled. If Hi-Z
= 1 the output is placed in a high impedance condition OE (Pin 4/Pin 1): Output Enable. Drive high to enable the
when disabled. output driver (Pin 6). Driving OE low disables the output
asynchronously, so that the output is immediately forced
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage low (Hi-Z = 0) or floated (Hi-Z = 1). When enabled, the
on the SET pin (VSET) is regulated to 1V above GND. The output may temporarily remain low to synchronize with
amount of current sourced from the SET pin (ISET) pro- the internal oscillator in order to eliminate pulse slivers.
grams the master oscillator frequency. The ISET current
range is 1.25µA to 40µA. The output oscillation will stop GND (Pin 5/Pin 2): Ground. Tie to a low inductance
if ISET drops below approximately 500nA. A resistor con- ground plane for best performance.
nected between SET and GND is the most accurate way to OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
set the frequency. For best performance, use a precision from GND to V+ with an output resistance of approximately
metal or thin film resistor of 0.5% or better tolerance 30Ω. When driving an LED or other low-impedance load
and 50ppm/°C or better temperature coefficient. For lower a series output resistor should be used to limit source/
accuracy applications an inexpensive 1% thick film resis- sink current to 20mA.
tor may be used.

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 LTC6990
BLOCK DIAGRAM (S6 Package Pin Numbers Shown)

V+ OE
5 1

R1 Hi-Z BIT
DIV
4-BIT A/D DIGITAL
4
CONVERTER FILTER
R2
Hi-Z WHEN
DISABLED
MASTER OSCILLATOR
1µs VSET OUT
t MASTER = • MCLK
50kΩ ISET PROGRAMMABLE DIVIDER
6
÷1, 2, 4, 8, 16, 32, 64, 128

tOUT

HALT OSCILLATOR Hi-Z OUTPUT

IF ISET < 500nA UNTIL SETTLED

ISET

+ POR

–
+ 1V
– VSET = 1V

2 3
6990 BD
GND SET

RSET

Rev. D

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LTC6990
OPERATION
The LTC6990 is built around a master oscillator with a DIVCODE
1MHz maximum frequency. The oscillator is controlled The DIV pin connects to an internal, V+ referenced 4-bit
by the SET pin current (ISET) and voltage (VSET), with a A/D converter that monitors the DIV pin voltage (VDIV) to
1MHz • 50k conversion factor that is accurate to ±0.8% determine the DIVCODE value. DIVCODE programs two
under typical conditions. settings on the LTC6990:
1 I
f MASTER = = 1MHz • 50k • SET 1. DIVCODE determines the output frequency divider set-
t MASTER VSET ting, NDIV.
A feedback loop maintains VSET at 1V ±30mV, leaving ISET 2. DIVCODE determines the state of the output when dis-
as the primary means of controlling the output frequency. abled, via the Hi-Z bit.
The simplest way to generate ISET is to connect a resistor VDIV may be generated by a resistor divider between V+
(RSET) between SET and GND, such that ISET = VSET/RSET. and GND as shown in Figure 1.
The master oscillator equation reduces to:
1 1MHz • 50k 2.25V TO 5.5V
f MASTER = =
t MASTER R SET V+
LTC6990 R1
From this equation it is clear that VSET drift will not affect
DIV
the output frequency when using a single program resis-
R2
tor (RSET). Error sources are limited to RSET tolerance and
GND
the inherent frequency accuracy ∆fOUT of the LTC6990. 6990 F01

RSET values between 50k and 800k (equivalent to ISET

between 1.25µA and 20µA) produce the best results, Figure 1. Simple Technique for Setting DIVCODE
although RSET may be reduced to 25k (ISET = 40µA) with
reduced accuracy.
The LTC6990 includes a programmable frequency divider
which can further divide the frequency by 1, 2, 4, 8, 16,
32, 64 or 128 before driving the OUT pin. The divider ratio
NDIV is set by a resistor divider attached to the DIV pin.
1 1MHz • 50k ISET
fOUT = = •
t OUT NDIV VSET

With RSET in place of VSET /ISET the equation reduces to:

1 1MHz • 50k
fOUT = =
t OUT NDIV • R SET

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 LTC6990
OPERATION
Table 1. DIVCODE Programming
DIVCODE Hi-Z NDIV Recommended fOUT R1 (k) R2 (k) VDIV /V+
0 0 1 62.5kHz to 1MHz Open Short ≤ 0.03125 ±0.015
1 0 2 31.25kHz to 500kHz 976 102 0.09375 ±0.015
2 0 4 15.63kHz to 250kHz 976 182 0.15625 ±0.015
3 0 8 7.813kHz to 125kHz 1000 280 0.21875 ±0.015
4 0 16 3.906kHz to 62.5kHz 1000 392 0.28125 ±0.015
5 0 32 1.953kHz to 31.25kHz 1000 523 0.34375 ±0.015
6 0 64 976.6Hz to 15.63kHz 1000 681 0.40625 ±0.015
7 0 128 488.3Hz to 7.813kHz 1000 887 0.46875 ±0.015
8 1 128 488.3Hz to 7.813kHz 887 1000 0.53125 ±0.015
9 1 64 976.6Hz to 15.63kHz 681 1000 0.59375 ±0.015
10 1 32 1.953kHz to 31.25kHz 523 1000 0.65625 ±0.015
11 1 16 3.906kHz to 62.5kHz 392 1000 0.71875 ±0.015
12 1 8 7.813kHz to 125kHz 280 1000 0.78125 ±0.015
13 1 4 15.63kHz to 250kHz 182 976 0.84375 ±0.015
14 1 2 31.25kHz to 500kHz 102 976 0.90625 ±0.015
15 1 1 62.5kHz to 1MHz Short Open ≥ 0.96875 ±0.015

Table 1 offers recommended 1% resistor values that accu- column in Table 1 shows the ideal ratio of VDIV to the
rately produce the correct voltage division as well as the supply voltage, which can also be calculated as:
corresponding NDIV and Hi-Z values for the recommended
VDIV DIVCODE + 0.5
resistor pairs. Other values may be used as long as: = ± 1.5%
+ 16
V
1. The VDIV /V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects) For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
2. The driving impedance (R1||R2) does not exceed 500kΩ.
Figure 2 illustrates the information in Table 1, showing
If the voltage is generated by other means (i.e. the output
that NDIV is symmetric around the DIVCODE midpoint.
of a DAC) it must track the V+ supply voltage. The last
On start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. If VDIV

Hi-Z BIT = 0 Hi-Z BIT = 1

1000
0 15
1 14
100
fOUT (kHz)

2 13
3 12
4 11
10 5 10
6 9
7 8
1
RECOMMENDED RANGE
EXTENDED RANGE
0.1
0V 0.5• V+ V+
INCREASING VDIV
6990 F02

Figure 2. Frequency Range and Hi-Z Bit vs DIVCODE

Rev. D

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LTC6990
OPERATION
is not stable, it will increase the start-up time as the con- Figure 3 illustrates the timing for the OE function when
verter waits for a stable result. Therefore, capacitance on Hi-Z = 0. When OE is low, the output is disabled and OUT
the DIV pin should be minimized so it will settle quickly. is held low. Bringing OE high enables the output after a
Less than 100pF will not affect performance. delay, tENABLE, which synchronizes the enable to eliminate
sliver pulses and guarantee the correct width for the first
Output Enable pulse. If NDIV = 1 or 2 this delay will be no longer than the
The OE pin controls the state of the LTC6990’s output as output period, tOUT. If NDIV > 2 the delay is limited to twice
seen on the OUT pin. Pulling the OE pin high enables the the internal master oscillator period (or 2 • tMASTER).
oscillator output. Pulling it low disables the output. When Forcing OE low will bring OUT low after a propagation
the output is disabled, it is either held low or placed in delay, tPD. If the output is high when OE falls, the output
a high impedance state as dictated by the Hi-Z bit value pulse will be truncated.
(determined by the DIVCODE as described earlier). Table 2 As shown in Figure 4, setting Hi-Z = 1 places the output in
summarizes the output control states. a high-impedance state when OE = 0. This feature allows
Table 2. Output States
for “wired-OR” connections of multiple devices. Driving
OE high enables the output. The output will usually be
OE Pin Hi-Z OUT
forced low during this time, although it is possible for
1 X Enabled, Output is Active
OUT to transition directly from high-impedance to a high
0 1 Disabled, Output is Hi-Z
output, depending on the timing of the OE transition rela-
0 0 Disabled, Output is Held Low
tive to the internal oscillator. Once high, the first output
pulse will have the correct width (unless truncated by
bringing OE low again).

OE
tPD tPD

OUT
tENABLE
tOUT tENABLE
6990 F03

Figure 3. OE Timing Diagram (Hi-Z = 0)

OE
tPD tPD tPD tPD

Hi-Z
OUT

tENABLE
tOUT tENABLE
6990 F04

Figure 4. OE Timing Diagram (Hi-Z = 1)

Rev. D

12 For more information www.analog.com

 LTC6990
OPERATION
Changing DIVCODE After Start-Up Start-Up Time
Following start-up, the A/D converter will continue moni- When power is first applied to the LTC6990 the power-on
toring VDIV for changes. Changes to DIVCODE will be reset (POR) circuit will initiate the start-up time, tSTART.
recognized slowly, as the LTC6990 places a priority on The OUT pin is floated (high-impedance) during this time.
eliminating any “wandering” in the DIVCODE. The typi- The typical value for tSTART ranges from 0.5ms to 8ms
cal delay depends on the difference between the old and depending on the master oscillator frequency (indepen-
new DIVCODE settings and is proportional to the master dent of NDIV):
oscillator period.
t START(TYP) = 500 • t MASTER
t DIVCODE = 16 • (∆DIVCODE + 6) • t MASTER
The start-up time may be longer if the supply or DIV
A change in DIVCODE will not be recognized until it is pin voltages are not stable. For this reason, it is recom-
stable, and will not pass through intermediate codes. A mended to minimize the capacitance on the DIV pin so it
digital filter is used to guarantee the DIVCODE has settled will properly track V+.
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.

576µs
DIV
1V/DIV V+
1V/DIV

470µs
OUT
OUT
1V/DIV
1V/DIV OUTPUT CONNECTED
TO 1.25V THROUGH 25k
TO SHOW Hi-Z
6990 F05
100µs/DIV 100µs/DIV 6990 F06

V+ = 3.3V V+ = 2.5V
RSET = 200k DIVCODE = 4
RSET = 50k

Figure 5. DIVCODE Change from 5 to 2 Figure 6. Typical Start-Up

Rev. D

For more information www.analog.com 13

LTC6990
APPLICATIONS INFORMATION
OE

Hi-Z
OUT

1/2 tOUT
tSTART tOUT
6990 F07

Figure 7. Start-Up Timing Diagram (OE = 1, NDIV = 1 or 2, Hi-Z = 0 or 1)

OE

Hi-Z
OUT

tSTART tMASTER tOUT

6990 F08

Figure 8. Start-Up Timing Diagram (OE = 1, NDIV ≥ 4, Hi-Z = 0 or 1)

OE

Hi-Z
OUT

tENABLE
tSTART tOUT
6990 F09

Figure 9. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 0)

OE

tPD

Hi-Z
OUT

tSTART REMAINS Hi-Z tENABLE tOUT

UNTIL OE = 1 6990 F10

Figure 10. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 1)

Rev. D

14 For more information www.analog.com

 LTC6990
APPLICATIONS INFORMATION
Start-Up Behavior Step 2: Calculate and Select RSET
When first powered up, the output is high impedance. If The final step is to calculate the correct value for RSET
the output is enabled (OE = 1) at the end of the start-up using the following equation.
time, the output will go low for one tMASTER cycle (or half 1MHz • 50k
a tOUT cycle if NDIV < 4) before the first rising edge. If the R SET = (1b)
NDIV • fOUT
output is disabled (OE = 0) at the end of the start-up time,
the output will drop to a low output if the Hi-Z bit = 0, or Select the standard resistor value closest to the calculated
simply remain floating if Hi-Z = 1. value.
Basic Fixed Frequency Operation Example: Design a 20kHz Oscillator with Minimum
The simplest and most accurate method to program the Power Consumption
LTC6990 for fixed frequency operation is to use a sin-
gle resistor, RSET, between the SET and GND pins. The Step 1: Selecting the NDIV Frequency Divider Value
design procedure is a simple two step process. First select First, choose an NDIV value that meets the requirements
the NDIV value and then calculate the value for the RSET of Equation (1a).
resistor.
3.125 ≤ NDIV ≤ 50
Alternatively, Analog Devices offers the easy to use
Potential settings for NDIV include 4, 8, 16, and 32. NDIV
TimerBlox Designer tool to quickly design any LTC6990
= 4 is the best choice, as it minimizes supply current by
based circuit. Use the free TimerBlox LTC6990: Voltage
using a large RSET resistor. Using Table 1, choose the R1
Controlled Oscillator Web-Based Design Tool.
and R2 values to program DIVCODE to either 2 or 13,
Step 1: Selecting the NDIV Frequency Divider Value depending on the desired behavior when the output is
disabled.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the Hi-Z bit and the Step 2: Select RSET
NDIV value. For a given output frequency, NDIV should be Calculate the correct value for RSET using Equation (1b).
selected to be within the following range.
1MHz • 50k
62.5kHz 1MHz R SET = = 625k
≤ NDIV ≤ (1a) 4 • 20kHz
fOUT fOUT
Since 625k is not available as a standard 1% resistor,
To minimize supply current, choose the lowest NDIV value substitute 619k if a 0.97% frequency shift is acceptable.
(generally recommended). For faster start-up or decreased Otherwise, select a parallel or series pair of resistors such
jitter, choose a higher NDIV setting. Alternatively, use as 309k and 316k to attain a more precise resistance.
Table 1 as a guide to select the best NDIV value for the
given application. After choosing the value for NDIV, use
Table 1 to select the proper resistor divider or VDIV/V+
ratio to apply to the DIV pin.

Rev. D

For more information www.analog.com 15

LTC6990
APPLICATIONS INFORMATION
Frequency Modulated Operation (Voltage-Controlled fOUT, choose a value for NDIV that meets the following
Oscillator) conditions
Operating the LTC6990 as a voltage-controlled oscillator 62.5kHz 1MHz
in its simplest form is achieved with one additional resis- ≤ NDIV ≤ (3a)
fOUT(MIN) fOUT(MAX)
tor. As shown in Figure 11, voltage VCTRL sources/sinks
a current through RVCO to vary the ISET current, which The 16:1 frequency range of the master oscillator and
in turn modulates the output frequency as described in the 2:1 divider step-size provides several overlapping fre-
Equation (2). quency spans to guarantee that any 8:1 modulation range
can be covered by a single NDIV setting. RVCO allows the
1MHz • 50k ⎛ R VCO VCTRL ⎞ gain to be tailored to the application, mapping the VCTRL
fOUT = • 1+ – (2)
NDIV •R VCO ⎜⎝ RSET VSET ⎟⎠ voltage range to the modulation range.
V+
Step 2: Calculate KVCO and f(0V)
OE OUT
LTC6990 V+ KVCO and f(0V) define the VCO’s transfer function and sim-
GND V+
C1
plify the calculation of the the RVCO and RSET resistors.
RVCO
0.1µF R1 Calculate these parameters using the following equations.
VCTRL SET DIV
fOUT(MAX) – fOUT(MIN)
RSET 6990 F08 R2 K VCO = (3b)
VCTRL(MAX) – VCTRL(MIN)

Figure 11. Voltage Controlled Oscillator f(0V) = fOUT(MAX) + KVCO • VCTRL(MIN) (3c)
Equation (2) can be re-written as shown below, where KVCO and f(0V) are not device settings or resistor values
f(0V) is the output frequency when VCTRL = 0V, and KVCO themselves. However, beyond their utility for the resistor
is the frequency gain. Note that the gain is negative (the calculations, these parameters provide a useful and intui-
output frequency decreases as VCTRL increases). tive way to look at the VCO application. The f(0V) param-
eter is the output frequency when VCTRL is at 0V. Viewed
fOUT = f(0V) – K VCO • VCTRL another way, it is the fixed output frequency when the
RVCO and RSET resistors are in parallel. KVCO is actually
1MHz • 50k the frequency gain of the circuit.
f(0V) =
NDIV • (R SET R VCO )
With KVCO and f(0V) determined, the RVCO and RSET values
1MHz • 50k can now be calculated.
K VCO =
NDIV • VSET • R VCO Step 3: Calculate and Select RVCO

The next step is to calculate the correct value for RVCO
The design procedure for a VCO is a simple four step
using the following equation.
process. First select the NDIV value. Then calculate the
intermediate values KVCO and f(0V). Next, calculate and 1MHz • 50k
R VCO = (3d)
select the RVCO resistor. Finally calculate and select the NDIV • VSET • K VCO
RSET resistor.
Select the standard resistor value closest to the calculated
Step 1: Select the NDIV Frequency Divider Value value.
For best accuracy, the master oscillator frequency should
fall between 62.5kHz and 1MHz. Since fMASTER = NDIV •
Rev. D

16 For more information www.analog.com

 LTC6990
APPLICATIONS INFORMATION
Step 4: Calculate and Select RSET frequency range applications (high KVCO) can have fre-
The final step is to calculate the correct value for RSET quency errors greater than ±50% at the highest VCTRL
using the following equation: voltage (lowest fOUT). For this reason the simple, two
resistor VCO circuit must be used with caution for appli-
1MHz • 50k cations where the frequency range is greater than 4:1.
R SET = (3e)
(
NDIV • f(0V) – VSET • K VCO ) Restricting the range to 4:1 typically keeps the frequency
error due to VSET variation below 10%.
Select the standard resistor value closest to the calculated
value. For wide frequency range applications, the non-invert-
ing VCO circuit shown in Figure 13 is preferred because
Some applications require combinations of fOUT(MIN), the maximum frequency error occurs when the fre-
fOUT(MAX), VCTRL(MIN) and VCTRL(MAX) that are not achiev- quency is highest, keeping the relative error (in percent)
able. These applications result in unrealistic or unrealiz- much smaller.
able (e.g. negative value) resistors. These applications
will require preconditioning of the VCTRL signal via range 100
scaling and/or level shifting to place the VCTRL into a range
that yields realistic resistor values. 80

Frequency Error in VCO Applications Due to VSET Error fOUT (kHz) 60

As stated earlier, f(0V) represents the frequency for VCTRL

= 0V, which is the same value as would be generated by 40

a single resistor between SET and GND with a value of

20
RSET || RVCO . Therefore, f(0V) is not affected by error or
drift in VSET (i.e. ΔVSET adds no frequency error when
0
VCTRL = 0V). 1 2 3 4
VCTRL (V)
The accuracy of KVCO does depend on VSET because 6990 F12

the output frequency is controlled by the ratio of VCTRL Figure 12. VCO Transfer Function
to VSET. The frequency error (in Hertz) due to ΔVSET is
approximated by:
Example: Design a VCO with the Following Parameters
∆V
∆fOUT ≅ K VCO • VCTRL • SET fOUT(MAX) = 100kHz at VCTRL(MIN) = 1V
VSET
fOUT(MIN) = 10kHz at VCTRL(MAX) = 4V
As the equation indicates, the potential for error in output
frequency due to VSET error increases with KVCO and is Step 1: Select the NDIV Value
at its largest when VCTRL is at its maximum. Recall that First, choose an NDIV that meets the requirements of
when VCTRL is at its maximum, the output frequency is Equation (3a).
at its minimum. With the maximum absolute frequency
error (in Hertz) occurring at the lowest output frequency, 6.25 ≤ NDIV ≤ 10
the relative frequency error (in percent) can be significant. The application’s desired frequency range is 10:1, which
VSET is nominally 1.0V with a maximum error of ±30mV isn’t always possible. However, in this case NDIV = 8 meets
for at most a ±3% error term. However, this ±3% potential both requirements of Equation (3).
error term is multiplied by both VCTRL and KVCO. Wide

Rev. D

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LTC6990
APPLICATIONS INFORMATION
Step 2: Calculate KVCO and f(0V) In this design example, with its wide 10:1 frequency
Next, calculate the intermediate values KVCO and f(0V) range, the potential output frequency error due to VSET
using Equations (3b) and (3c). error alone ranges from less than ±1% when VCTRL is at
its minimum up to ±36% when VCTRL is at its maximum.
100kHz −10kHz This error must be accounted for in the system design.
K VCO = = 30kHz/V
4V −1V
Depending on the application’s requirements, the non-
f(0V) = 100kHz + 30kHz/V •1V = 130kHz inverting VCO circuit in Figure 13 may be preferred for
this wide of a frequency variation as its maximum inac-
Step 3: Calculate and Select RVCO curacy due to VSET error is only ±9% and can be reduced
to only ±3% with a small change to the voltage tuning
The next step is to use Equation (3d) to calculate the cor-
range specification.
rect value for RVCO.
1MHz • 50k Reducing VSET Error Effects in VCO Applications
R VCO = = 208.333k
8 • 1V • 30kHz/V Figure 13 shows a VCO that reduces the effect of ΔVSET
Select RVCO = 210k. by adding an op-amp to make VCTRL dependent on VSET.
This circuit also has a positive transfer function (the out-
Step 4: Calculate and Select RSET put frequency increases as VIN increases). Furthermore,
for positive VIN voltages, this circuit places the greatest
The final step is to calculate the correct value for RSET absolute frequency error at the highest output frequency.
using Equation (3e). Compared to the simple VCO circuit of Figure 11, the
1MHz • 50k absolute frequency error is unchanged. However, with the
RSET = = 62.5k maximum absolute frequency error (in Hertz) now occur-
8 • (130kHz −1V • 30kHz/V )
ring at the highest output frequency, the relative frequency
Select RSET = 61.9k error (in percent) is greatly improved.

10kHz TO 100kHz
3V fOUT

OE OUT
LTC6990 3V

GND V+
C1 R1
0.1µF 1M
VSET
SET DIV DIVCODE = 3
3V (NDIV = 8, Hi-Z = 0)
6990 F13
R2
+ RVCO
VCTRL 75k 280k
1/2
R3
LTC6078
0.4V TO 4V 100k
VIN – RSET
249k 1MHz • 50k! ) R VCO # VIN & R4 ,
fOUT = •+ + "1 • .
R4 NDIV •R VCO * RSET %$ VSET (' R3 -
30.1k
R4 R VCO
IF = , THE EQUATION REDUCES TO:
C4 R3 RSET
33pF
1MHz • 50k! VIN
fOUT = • = VIN • 25kHz/V
NDIV •RSET VSET

Figure 13. VCO with Reduced ∆VSET Sensitivity

Rev. D

18 For more information www.analog.com

 LTC6990
APPLICATIONS INFORMATION
Additionally, by choosing the VCO’s specifications ISET Extremes (Master Oscillator Frequency Extremes)
shrewdly, the frequency error (in percent) due to VSET Pushing ISET outside of the recommended 1.25µA to 20µA
variation is reduced to ΔVSET/VSET = ±3%. To realize this range forces the master oscillator to operate outside of
improvement, the design must abide by three condi- the 62.5kHz to 1MHz range in which it is most accurate.
tions. First, the VIN voltage must be positive throughout The oscillator will still function with reduced accuracy
the range. Second, choose VMAX /VMIN ≥ fMAX /fMIN. Last, in its extended range (see the Electrical Characteristics
choose RVCO /RSET ≥ R4/R3. section).
Figure 13 shows a design similar to the previous design The LTC6990 is designed to function normally for ISET
example where the VMIN voltage is now specified to be as low as 1.25µA. At approximately 500nA, the oscillator
0.4V. This satisfies the VMAX /VMIN ≥ fMAX /fMIN condition output will be frozen in its current state. For NDIV = 1 or 2,
and the design assures that the output frequency error OUT will halt in a low state. But for larger divider ratios,
due to VSET variation is only ±3%. it could halt in a high or low state. This avoids introduc-
Eliminating VSET Error Effects with DAC Frequency ing short pulses while modulating a very low frequency
Control output. Note that the output will not be disabled as when
OE is low (e.g. the output will not enter a high impedance
Many DACs allow for the use of an external reference. state if Hi-Z = 1).
If such a DAC is used to provide the VCTRL voltage, the
VSET error is eliminated by buffering VSET and using it as At the other extreme, the master oscillator frequency can
the DAC’s reference voltage, as shown in Figure 14. The reach 2MHz for ISET = 40μA (RSET = 25k). It is not recom-
DAC’s output voltage now tracks any VSET variation and mended to operate the master oscillator beyond 2MHz
eliminates it as an error source. The SET pin cannot be because the accuracy of the DIV pin ADC will suffer.
tied directly to the reference input of the DAC because
the current drawn by the DAC’s REF input would affect
the frequency.

OE OUT
LTC6990 V+

GND V+
C1
V+ 0.1µF R1

+ SET DIV
1/2
LTC6078 6990 F14
R2
–

V+

1MHz • 50k! # R VCO DIN &

VCC REF fOUT = • 1+ "
DIN NDIV •R VCO %$ RSET 4096 ('
RVCO
µP CLK LTC1659 VOUT DIN = 0 to 4095

CS/LD RSET
GND

Figure 14. Digitally Controlled Oscillator with VSET Variation Eliminated

Rev. D

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LTC6990
APPLICATIONS INFORMATION
Modulation Bandwidth and Settling Time Power Supply Current
The LTC6990 will respond to changes in ISET up to a –3dB The power supply current varies with frequency, supply
bandwidth of 0.4 • fOUT (see Figure 15). This makes it easy voltage and output loading. It can be estimated under any
to stabilize a feedback loop around the LTC6990, since it condition using the following equation:
does not introduce a low-frequency pole.
Settling time depends on the master oscillator frequency. IS(TYP) ≈ V + • fMASTER • 7pF + V + • f OUT •(13pF +CLOAD )
Following a 2x or 0.5x step change in ISET, the output
frequency takes approximately six master clock cycles V+ V+
(6 • tMASTER) to settle to within 1% of the final value. An + + +1.75 •ISET + 50µA
480kΩ 2 •RLOAD
example is shown in Figure 16.

The equation is also valid for OE = 0 (output disabled),

0 with fOUT = 0Hz.
VCTRL = 0.536V + 0.278V
• SIN(2π•fMOD •t)
fOUT =18.75kHz ±10%
VCTRL
∆fOUT (fMOD)/∆fOUT(DC) (dB)

–10 2V/DIV
–3dB AT 0.4•fOUT
OUT
2V/DIV
–20

–30 fOUT
RSET = 200k 50kHz/DIV
RVCO = 464k
DIVCODE = 4(÷16)
–40
0.1 1 10 10µs/DIV 6990 F16

fMOD /fOUT (Hz/Hz) V+ = 3.3V, DIVCODE = 0

6990 F15 RSET = 200k, RVCO = 464k
fOUT = 175kHz AND 350kHz
Figure 15. Modulation Frequency Response
Figure 16. Settling Time

Rev. D

20 For more information www.analog.com

 LTC6990
APPLICATIONS INFORMATION
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES plane and the C1 connection to the ground plane are
recommended to minimize the inductance. Capacitor
The LTC6990 is a 2.2% accurate silicon oscillator when
C1 should be a 0.1µF ceramic capacitor.
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance 2. Place all passive components on the top side of the
is easily achieved. The most important use issues involve board. This minimizes trace inductance.
adequate supply bypassing and proper PCB layout. 3. Place RSET as close as possible to the SET pin and
Figure 17 shows example PCB layouts for both the SOT-23 make a direct, short connection. The SET pin is a cur-
and DCB packages using 0603 sized passive components. rent summing node and currents injected into this pin
The layouts assume a two layer board with a ground plane directly modulate the operating frequency. Having a
layer beneath and around the LTC6990. These layouts are short connection minimizes the exposure to signal
a guide and need not be followed exactly. pickup.
1. Connect the bypass capacitor, C1, directly to the V+ and 4. Connect RSET directly to the GND pin. Using a long path
GND pins using a low inductance path. The connection or vias to the ground plane will not have a significant
from C1 to the V+ pin is easily done directly on the top affect on accuracy, but the direct, short connection is
layer. For the DCB package, C1’s connection to GND recommended and easy to apply.
is also simply done on the top layer. For the SOT-23, 5. Use a ground trace to shield the SET pin. This provides
OUT can be routed through the C1 pads to allow a good another layer of protection from radiated signals.
C1 GND connection. If the PCB design rules do not
allow that, C1’s GND connection can be accomplished 6. Place R1 and R2 close to the DIV pin. A direct, short
through multiple vias to the ground plane. Multiple connection to the DIV pin minimizes the external signal
vias for both the GND pin connection to the ground coupling.

OE OUT
LTC6990

GND V+ V+
C1
0.1µF R1

SET DIV

RSET R2

V+

R1 C1
C1 V+

V+ OUT OE OUT

DIV GND GND V+

R2 SET OE SET DIV
R1
RSET
RSET R2

DCB PACKAGE TSOT-23 PACKAGE

6990 F17

Figure 17. Supply Bypassing and PCB Layout

Rev. D

For more information www.analog.com 21

LTC6990
TYPICAL APPLICATIONS
Programming NDIV Using an 8-Bit DAC

DIVCODE DAC CODE

OE OUT 0 0
1 24
LTC6990 2.25V TO 5.5V 2 40
3 56
GND V+ 4 72
C1
5 88
0.1µF
6 104
SET DIV 7 120
C2 8 136
RSET 0.1µF VCC 9 152
619k SDI 10 168
11 184
VOUT LTC2630-LZ8 SCK µP 12 200
13 216
CS/LD 14 232
GND 15 255
6990 TA02

Full Range VCO with Any NDIV Setting (fMAX to fMIN for VIN = 0V to VSET)

5V
RVCO2
26.1k OE OUT
LTC6990
5V
RVCO1
D1 GND V+ 5V
26.1k – C1
VIN IN4148 0.1µF R1
0V TO 1V
LT1490 SET DIV
+ 6990 TA03
R2

RSET
826k

Full Range VCO with Any NDIV Setting (Positive Frequency Control, fMIN to fMAX for VIN = 0V to VSET

5V
R4
10k OE OUT
LTC6990
5V
R3 GND V+ 5V
10k – C1
VIN RVCO 0.1µF R1
0V TO 1V 53.6k
LT1490 SET DIV
+ 6990 TA04
R2
RSET1
412k

RSET2
412k

Rev. D

22 For more information www.analog.com

 LTC6990
TYPICAL APPLICATIONS
Speaker Alarm. Modulate Tone with RVCO within 500Hz to 8kHz Span

5V

IN4004 8Ω
5V

20k
OE OUT 2N2222
LTC6990 50k

GND V+ 5V
1M
RVCO
STEP
SET DIV
RAMP 6990 TA05
97.6k 887k

Overvoltage Detector/Alarm. Direct Drive of Piezo Alarm

24V
5V
RA
787k
+ 100k
RB LT6703-3
10.7k OE OUT
400mV – LTC6990 PIEZO ALARM
4kHz
+ 5V
GND V MURATA
PKM29-3A0
1M
⎛ R ⎞ SET DIV
V ALARM = 400mV ⎜ 1+ A ⎟ = 30V
⎝ RB ⎠
6990 TA06
392k 523k

Rev. D

For more information www.analog.com 23

LTC6990
TYPICAL APPLICATIONS
Direct Piezo Alarm Driver. Adjust Frequency for Maximum Alarm Sound Pressure
(Maximum Annoyance for Best Effect)

5V

ON 10k
OE OUT
OFF LTC6990 PIEZO ALARM
MURATA
GND V+ 5V PKM29-340
f = 4kHz
1M

SET DIV
6990 TA07
392k 523k

Isolated V → F Converter. VIN Provided by Isolated Measurement Circuit.

5µs Rise/Fall Time of Isolator Limits fMAX to 60kHz

5V 3.3V
365Ω
MOC207M
OE OUT
LTC6990

GND V+ 5V
1M
75k 412Ω fOUT
VIN
0V TO 5V SET DIV
6990 TA08
157k 523k

Rev. D

24 For more information www.analog.com

 LTC6990
TYPICAL APPLICATIONS
Quadrature Sine Wave Oscillator. Voltage Controlled Frequency Range
from ~5Hz to ~20kHz with 1VP-P Constant Output Amplitude

1.18VREF SINE COSINE

51.1k

5.11k
2 N 4 S1 1 BP 14 LP
INV1 5V
3
– LTC1059*
+ –
124k
+ –
8 CLOCK

5V
5 SA 11 AGND 9 50/100
2.5V FOR 5Hz TO 10kHz OUT OE
10k 5V FOR 10Hz TO 20kHz
LTC6990
2.5V
2k
5V LT1004-2.5V 5V V+ GND
1M
R1 RVCO
1M 267k
DIV SET FREQ
VCC – ADJ
OUT R2 RSET
LTC1440 280k 49.9k
V– + 6990 TA09

*1/2 OF AN LTC1060 FILTER CAN

1.18VREF HYST BE USED IN PLACE OF THE LTC1059

4.12k 0.1µF

1M

Temperature to Frequency Converter.

3% Linearity from –20°C (fOUT ≈ 20kHz) to 75°C (fOUT ≈ 25kHz)

5V

OE OUT fOUT
LTC6990

GND V+ 5V
1M
60.4k
SET DIV
22k AT 25°C 6990 TA10
21.5k 523k
B = 3964
+

THERMISTOR: VISHAY NTHS120601N2202J

Rev. D

For more information www.analog.com 25

LTC6990
TYPICAL APPLICATIONS
Full Range Temperature to Frequency Converter. 16kHz to 1kHz from –20°C to 80°C

5V

OE OUT fOUT
10k LTC6990

5V GND V+ 5V
–
1M
100k
LT1490 SET DIV
22k AT 25°C
+ 6990 TA11
10k 681k
B = 3964
+ 26k

26k

THERMISTOR: VISHAY NTHS120601N2202J

Light to Frequency Converter. fOUT ≈ –1.4kHz per Microampere of Photo Diode Current, IPD

1000pF 5V

OE OUT fOUT
24.9k LTC6990

IPD 5V GND V+ 5V
–
187k
222k
LT1677 SET DIV
SFH213
+ 6990 TA12
619k 1M

Rev. D

26 For more information www.analog.com

 LTC6990
PACKAGE DESCRIPTION

DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)

0.70 ±0.05

1.65 ±0.05
3.55 ±0.05
(2 SIDES)
2.15 ±0.05
PACKAGE
OUTLINE

0.25 ±0.05
0.50 BSC
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

2.00 ±0.10 R = 0.115 0.40 ±0.10

(2 SIDES) TYP
R = 0.05 4 6
TYP

3.00 ±0.10 1.65 ±0.10

(2 SIDES) (2 SIDES)

PIN 1 BAR PIN 1 NOTCH

TOP MARK R0.20 OR 0.25
(SEE NOTE 6) × 45° CHAMFER
(DCB6) DFN 0405
3 1
0.25 ±0.05
0.200 REF 0.75 ±0.05 0.50 BSC
1.35 ±0.10
(2 SIDES)
0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

Rev. D

For more information www.analog.com 27

LTC6990
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)

0.62 0.95 2.90 BSC

MAX REF (NOTE 4)

1.22 REF

2.80 BSC 1.50 – 1.75

3.85 MAX 2.62 REF 1.4 MIN (NOTE 4)

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45

0.95 BSC
PER IPC CALCULATOR 6 PLCS (NOTE 3)

0.80 – 0.90

0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’

0.30 – 0.50 REF

0.09 – 0.20 1.90 BSC
(NOTE 3) S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193

Rev. D

28 For more information www.analog.com

 LTC6990
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 7/11 Updated Features, Description, Pin Configuration, and Order Information sections 1, 2
Added additional information to ∆fOUT/∆V+ and included Note 11 in Electrical Characteristics section 3, 4
Added Typical Frequency Error vs Time curve to Typical Performance Characteristics section 7
Modified drawing in SET pin description in Pin Functions 8
Added text to Basic Fixed Frequency Operation paragraph in Applications Information section 15
Updated Related Parts list 30
B 01/12 Added MP-grade 1, 2, 4
C 02/14 Web links added 1-30
Schematic edits to Quadrature Sine Wave Oscillator circuit 25
Edits to description of LTC6906 and LTC6907 (Related Parts) 30
D 01/20 Added AEC-Q100 Qualified Note to Front Page 1
Added W-Grade Order Information 2

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 29
LTC6990
TYPICAL APPLICATION
Ultrasonic Frequency Sweep Generator

fOUT = 500kHz TO 31.25kHz

OE OE OUT
LTC6990

GND V+ 2.25V TO 5.5V

C1 R1
0.1µF 976k
SET DIV

RSET1 6990 TA13 R2

74HC125 49.9k 102k

CSET RSET2
0.022µF 750k
SWEEPS FROM 500kHz to 31.25kHz IN A
FEW MILLISECONDS (CONTROLLED BY CSET).

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range
LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range
LTC6906 10kHz to 1MHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 12µA at 100kHz
LTC6907 40kHz to 4MHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35µA at 400kHz
LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
LTC6991 TimerBlox, Very Low Frequency Clock with Reset Cycle Time from 2ms to 9.5 Hours, No Caps, 2.2% Accurate
LTC6992 TimerBlox, Voltage-Controlled Pulse Width Modulator Simple PWM with Wide Frequency Range
(PWM)
LTC6993 TimerBlox, Monostable Pulse Generator Resistor Set Pulse Width from 1µs to 34sec, No Caps, 3% Accurate
LTC6994 TimerBlox, Delay Block/Debouncer Resistor Set Delay from 1µs to 34sec, No Caps Required, 3% Accurate

Rev. D

30
01/20
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