BU

BUF08832
F08
832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

Programmable Gamma-Voltage Generator and

High Slew Rate VCOM with Integrated Two-Bank Memory
Check for Samples: BUF08832

1FEATURES DESCRIPTION
•
23 10-BIT RESOLUTION The BUF08832 offers eight programmable gamma
• 8-CHANNEL P-GAMMA channels and one programmable VCOM channel.
• 1-CHANNEL P-VCOM The final gamma and VCOM values can be stored in
• HIGH SLEW RATE VCOM: 45V/μs the on-chip, nonvolatile memory. To allow for
programming errors or liquid crystal display (LCD)
• 16x REWRITABLE NONVOLATILE MEMORY
panel rework, the BUF08832 supports up to 16 write
• TWO INDEPENDENT PIN-SELECTABLE operations to the on-chip memory.
MEMORY BANKS
• RAIL-TO-RAIL OUTPUT The BUF08832 has two separate memory banks,
allowing simultaneous storage of two different gamma
– 300mV Min Swing-to-Rail (10mA) curves to facilitate switching between gamma curves.
– > 300mA Max IOUT
All gamma and VCOM channels offer a rail-to-rail
• LOW SUPPLY CURRENT
output that typically swings to within 150mV of either
• SUPPLY VOLTAGE: 9V to 20V supply rail with a 10mA load. All channels are
• DIGITAL SUPPLY: 2V to 5.5V programmed using a Two-Wire interface that
• TWO-WIRE INTERFACE: Supports 400kHz and supports standard operations up to 400kHz and
3.4MHz high-speed data transfers up to 3.4MHz.
The BUF08832 is manufactured using Texas
APPLICATIONS Instruments’ proprietary, state-of-the-art, high-voltage
• TFT-LCD REFERENCE DRIVERS CMOS process. This process offers very dense logic
and high supply voltage operation of up to 20V. The
Digital Analog
BKSEL (2.0V to 5.5V) (9V to 20V) BUF08832 is offered in a HTSSOP-20 PowerPAD™
package, and is specified from –40°C to +85°C.
1
BUF08832
RELATED PRODUCTS
FEATURES PRODUCT
OUT1 22-Channel Gamma Correction Buffer BUF22821
16-Channel Gamma Correction Buffer BUF16821
OUT2
12-Channel Gamma Correction Buffer BUF12800
¼
¼
¼
¼
¼
16x Nonvolatile Memory BANK0

18-/20-Channel Programmable Buffer, 10-Bit, VCOM BUF20800

16x Nonvolatile Memory BANK1

18-/20-Channel Programmable Buffer with Memory BUF20820

DAC Registers

DAC Registers

OUT7
Programmable VCOM Driver BUF01900
OUT8
18V Supply, Traditional Gamma Buffers BUF11704
22V Supply, Traditional Gamma Buffers BUF11705

VS (VCOM)

VCOM

GND (VCOM)

VCOM-FB

SDA
Control IF
SCL

A0

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PowerPAD is a trademark of Texas Instruments Incorporated.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION (1)

PRODUCT PACKAGE PACKAGE DESIGNATOR PACKAGE MARKING
BUF08832 HTSSOP-20 PWP BUF08832

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range (unless otherwise noted).
PARAMETER BUF08832 UNIT
Supply Voltage VS +22 V
Supply Voltage VSD +6 V
Digital Input Pins, SCL, SDA, AO, BKSEL: Voltage –0.5 to +6 V
Digital Input Pins, SCL, SDA, AO, BKSEL: Current ±10 mA
Output Pins, OUT1 through OUT16, VCOM1 and VCOM2 (2) (V–) – 0.5 to (V+) + 0.5 V
Output Short-Circuit (3) Continuous
Ambient Operating Temperature –40 to +95 °C
Ambient Storage Temperature –65 to +150 °C
Junction Temperature TJ +125 °C
Human Body Model HBM 4000 V
ESD Rating Charged Device Model CDM 1000 V
Machine Model MM 200 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) See the Output Protection section.
(3) Short-circuit to ground, one amplifier per package.

2 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TA = +25°C, VS = +18V, VSD = +2V, and CL = 200pF, unless otherwise noted.
BUF08832
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG GAMMA BUFFER CHANNELS
Reset Value Code 512 9 V
OUT 1, 8 Output Swing: High Code = 1023, Sourcing 10mA 17.7 17.85 V
OUT 1, 8 Output Swing: Low Code = 0, Sinking 10mA 0.07 0.3 V
OUT 2-7 Output Swing: High Code = 1023, Sourcing 10mA 17.5 17.85 V
OUT 2-7 Output Swing: Low Code = 0, Sinking 10mA 0.07 0.5 V
VCOM Output Swing: High (1) Sourcing/Sinking 400mA, G = 2 14 15.3 V
VCOM Output Swing: Low (1) Sourcing/Sinking 400mA, G = 2 3.8 5 V
VCOM Slew Rate (2) RLOAD = 60Ω, CLOAD = 100pF 45 V/μs
(3)
Continuous Output Current Note 30 mA
Output Accuracy (4) VCOM, codes 0 - 960; OUT 1 - 8, codes 0 - 1023 ±20 ±50 mV
vs Temperature Code 512 ±25 μV/°C
Integral Nonlinearity (4) INL 0.3 LSB
Differential Nonlinearity (4) DNL 0.3 LSB
Load Regulation, 10mA REG Code 512 or VCC/2, IOUT = +5mA to –5mA Step 0.5 1.5 mV/mA
OTP MEMORY
Number of OTP Write Cycles 16 Cycles
Memory Retention 100 Years
ANALOG POWER SUPPLY
Operating Range 9 20 V
Total Analog Supply Current IS Outputs at Reset Values, No Load 8.5 11 mA
Over Temperature 11 mA
DIGITAL
Logic 1 Input Voltage VIH 0.7 × VSD V
Logic 0 Input Voltage VIL 0.3 × VSD V
Logic 0 Output Voltage VOL ISINK = 3mA 0.15 0.4 V
Input Leakage ±0.01 ±10 μA
Clock Frequency fCLK Standard/Fast Mode 400 kHz
High-Speed Mode 3.4 MHz
DIGITAL POWER SUPPLY
Operating Range VSD 2.0 5.5 V
Digital Supply Current (3) ISD Outputs at Reset Values, No Load, Two-Wire Bus Inactive 115 180 μA
Over Temperature 115 μA
TEMPERATURE RANGE
Specified Range –40 +85 °C
Operating Range Junction Temperature < +125°C –40 +95 °C
Storage Range –65 +150 °C
Thermal Resistance (3) θJA
(5)
HTSSOP-20 See Note 40 °C/W

(1) The BUF08832 VCOM DAC limits can be programmed. These default limits apply if the device is not programmed. See the
Programmable VCOM Limit Section.
(2) See Figure 12, Large-Signal Step Response, VCOM.
(3) Observe maximum power dissipation.
(4) The VCOM output voltage is limited to codes 0 through 960; see Figure 3. This limitation is for VCOM only and does not affect DAC OUT,
1 through 8.
(5) Thermal pad attached to printed circuit board (PCB), 0lfm airflow, and 76mm × 76mm copper area.

Copyright © 2009–2011, Texas Instruments Incorporated 3

BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

PIN CONFIGURATION
PWP PACKAGE
HTSSOP-20
(TOP VIEW)

VCOM 1 20 VCOM-FB
(1)
GNDA 2 19 VS

OUT1 3 18 OUT8
PowerPAD
OUT2 4 Lead-Frame 17 OUT7
Die Pad
OUT3 5 16 OUT6
Exposed on
Underside OUT5
OUT4 6 15
(must connect to
(1)
VS 7 GNDA and GNDD) 14 GNDA
(1)
VSD 8 13 GNDD

SCL 9 12 BKSEL

SDA 10 11 A0

NOTE: (1) GNDA and GNDD must be connected together.

PIN DESCRIPTIONS
PIN # NAME DESCRIPTION
1 VCOM VCOM
2 GNDA Analog ground; must be connected to digital ground (GNDD).
3 OUT1 DAC output 1
4 OUT2 DAC output 2
5 OUT3 DAC output 3
6 OUT4 DAC output 4
7 VS VS connected to analog supply
8 VSD Digital supply; connect to logic supply
9 SCL Serial clock input; open-drain, connect to pull-up resistor.
10 SDA Serial data I/O; open-drain, connect to pull-up resistor.
11 A0 A0 address pin for Two-Wire address; connect to either logic 1 or logic 0. See Table 1.
12 BKSEL Selects memory bank 0 or 1; connect to either logic 1 to select bank 1 or logic 0 to select bank 0.
13 GNDD Digital ground; must be connected to analog ground at the BUF08832.
14 GNDA Analog ground; must be connected to digital ground (GNDD).
15 OUT5 DAC output 5
16 OUT6 DAC output 6
17 OUT7 DAC output 7
18 OUT8 DAC output 8
19 VS VS connected to analog supply
20 VCOM-FB VCOM feedback

4 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +18V, VSD = +2V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT
(VCOM) (Channels 1–8)
20 18.0
18 17.5
17.0
16
16.5
Output Voltage (V)

Output Voltage (V)

14 16.0 Output Swing High
12 15.5
15.0
10
3.0
8 2.5
6 2.0
1.5
4 Output Swing Low
1.0
2 0.5
0 0
0 50 100 150 200 250 250 250 400 0 25 50 75 100 125 150
Output Current (mA) Output Current (mA)

Figure 1. Figure 2.

VCOM OUTPUT VOLTAGE vs CODE ANALOG SUPPLY CURRENT HISTOGRAM

20 1200
Code 960
18
1000
16
Output Voltage (V)

14
800
Occurrence

12
10 600
8
400
6
4
VCOM output voltage limited to 200
2
codes 0 through 960.
0 0
0 128 256 384 512 640 768 896 1024 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Analog Supply Current (mA)
Code
Figure 3. Figure 4.

ANALOG SUPPLY CURRENT vs TEMPERATURE OUTPUT VOLTAGE vs TEMPERATURE

11.0 9.020
10 Typical Units Shown
10.5 9.015
Analog Supply Current (mA)

10.0
9.010
Initial Voltage (V)

9.5
9.005
9.0
9.000
8.5
8.995
8.0
7.5 8.990

7.0 8.985

6.5 8.980
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

Figure 5. Figure 6.

Copyright © 2009–2011, Texas Instruments Incorporated 5

BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = +18V, VSD = +2V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
DIGITAL SUPPLY CURRENT vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR
120 0.15
118
0.10
Digital Supply Current (mA)

116
114
0.05

Error (LSB)
112
110 0
108
-0.05
106
104
-0.10
102
100 -0.15
-50 -25 0 25 50 75 100 125 0 256 512 768 1024
Temperature (°C) Input Code

Figure 7. Figure 8.

INTEGRAL LINEARITY ERROR BKSEL SWITCHING TIME DELAY

0.15

0.10
BKSEL (2V/div)
0.05
Error (LSB)

780ms
0

9V
-0.05
DAC Channel
(2V/div)
-0.10
5V

-0.15
0 256 512 768 1024 1ms/div
Input Code

Figure 9. Figure 10.

LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE, VCOM

Output Voltage (3V/div)
Output Voltage (2V/div)

Time (2ms/div) Time (1ms/div)

Figure 11. Figure 12.

6 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

APPLICATION INFORMATION
GENERAL All slaves on the bus shift in the slave address byte
on the rising edge of SCL, with the last bit indicating
The BUF08832 programmable voltage reference whether a read or write operation is intended. During
allows fast and easy adjustment of eight the ninth clock pulse, the slave being addressed
programmable gamma reference outputs and a VCOM responds to the master by generating an
output, each with 10-bit resolution. The BUF08832 is Acknowledge and pulling SDA LOW.
programmed through a high-speed, Two-Wire
interface. The final gamma and VCOM values can be Data transfer is then initiated and eight bits of data
stored in the onboard, nonvolatile memory. To allow are sent, followed by an Acknowledge bit. During
for programming errors or liquid crystal display (LCD) data transfer, SDA must remain stable while SCL is
panel rework, the BUF08832 supports up to 16 write HIGH. Any change in SDA while SCL is HIGH is
operations to the onboard memory. The BUF08832 interpreted as a START or STOP condition.
has two separate memory banks, allowing
Once all data have been transferred, the master
simultaneous storage of two different gamma curves
generates a STOP condition, indicated by pulling
to facilitate dynamic switching between gamma
SDA from LOW to HIGH while SCL is HIGH. The
curves.
BUF08832 can act only as a slave device; therefore,
The BUF08832 can be powered using an analog it never drives SCL. SCL is an input only for the
supply voltage from 9V to 20V, and a digital supply BUF08832.
from 2V to 5.5V. The digital supply must be applied
before the analog supply to avoid excessive current ADDRESSING THE BUF08832
and power consumption, or possibly even damage to
the device if left connected only to the analog supply The address of the BUF08832 is 111010x, where x is
for extended periods of time. See Figure 13 and the state of the A0 pin. When the A0 pin is LOW, the
Figure 14 for typical configurations of the BUF08832. device acknowledges on address 74h (1110100). If
the A0 pin is HIGH, the device acknowledges on
address 75h (1110101). Table 1 shows the A0 pin
TWO-WIRE BUS OVERVIEW
settings and BUF08832 address options.
The BUF08832 communicates over an
Other valid addresses are possible through a simple
industry-standard, two-wire interface to receive data
mask change. Contact your TI representative for
in slave mode. This model uses a two-wire,
information.
open-drain interface that supports multiple devices on
a single bus. Bus lines are driven to a logic low level
Table 1. Quick Reference of BUF08832 Addresses
only. The device that initiates the communication is
called a master, and the devices controlled by the DEVICE/COMPONENT
master are slaves. The master generates the serial BUF08832 ADDRESS ADDRESS
clock on the clock signal line (SCL), controls the bus A0 pin is LOW
access, and generates the START and STOP 1110100
(device acknowledges on address 74h)
conditions. A0 pin is HIGH
1110101
To address a specific device, the master initiates a (device acknowledges on address 75h)
START condition by pulling the data signal line (SDA)
from a HIGH to a LOW logic level while SCL is HIGH.

Table 2. Quick Reference of Command Codes

COMMAND CODE
General-Call Reset Address byte of 00h followed by a data byte of 06h.
High-Speed Mode 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.

Copyright © 2009–2011, Texas Instruments Incorporated 7

BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

150W(1)

1.2kW(1)

34W(2) BUF08832
Panel 1 VCOM VCOM-FB 20

2 GNDA(3) VS(4) 19 VS
100nF 10mF

(5) (5)
3 OUT1 OUT8 18

(5) (5)
4 OUT2 OUT7 17
Source Source
Driver Driver
(5) (5)
5 OUT3 OUT6 16

(5) (5)
6 OUT4 OUT5 15

VS 7 VS(4) GNDA(3) 14

3.3V 8 VSD GNDD(3) 13

1mF 100nF

9 SCL BKSEL 12
Timing
Controller
10 SDA A0 11

(1) Values must be selected for the panel used.

(2) Values must be selected for good phase margin when driving large capacitive loads.
(3) GNDA and GNDD must be connected together.
(4) Pins 7 and 19 are VS. The one set of capacitors shown on pin 19 are common to both pins.
(5) RC combination for the OUT pins is not recommended; see the Output Protection section.

Figure 13. Typical Application Configuration (VCOM with Feedback)

8 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

BUF08832
1 VCOM VCOM-FB 20

2 GNDA(1) VS(2) 19 VS
100nF 10mF

(3) (3)
3 OUT1 OUT8 18

(3) (3)
4 OUT2 OUT7 17
Source Source
Driver Driver
(3) (3)
5 OUT3 OUT6 16

(3) (3)
6 OUT4 OUT5 15

VS 7 VS(4) GNDA(1) 14

3.3V 8 VSD GNDD(1) 13

1mF 100nF

9 SCL BKSEL 12
Timing
Controller
10 SDA A0 11

(1) GNDA and GNDD must be connected together.

(2) Pins 7 and 19 are VS. The one set of capacitors shown on pin 19 are common to both pins.
(3) RC combination for the OUT pins is not recommended; see the Output Protection section.

Figure 14. Typical Application Configuration (VCOM without Feedback)

Copyright © 2009–2011, Texas Instruments Incorporated 9

BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

DATA RATES OUTPUT VOLTAGE

The two-wire bus operates in one of three speed Buffer output values are determined by the analog
modes: supply voltage (VS) and the decimal value of the
• Standard: allows a clock frequency of up to binary input code used to program that buffer. The
100kHz; value is calculated using Equation 1:
• Fast: allows a clock frequency of up to 400kHz; CODE10
and VOUT = VS ´
1024
(1)
• High-speed mode (also called Hs mode): allows a
clock frequency of up to 3.4MHz. The BUF08832 outputs are capable of a full-scale
voltage output change in typically 5μs; no
The BUF08832 is fully compatible with all three
intermediate steps are required.
modes. No special action is required to use the
device in Standard or Fast modes, but High-speed
mode must be activated. To activate High-speed UPDATING THE DAC OUTPUT VOLTAGES
mode, send a special address byte of 00001 xxx, with Because the BUF08832 features a double-buffered
SCL ≤ 400kHz, following the START condition; where register structure, updating the digital-to-analog
xxx are bits unique to the Hs-capable master, which converter (DAC) and/or the VCOM register is not the
can be any value. This byte is called the Hs master same as updating the DAC and/or VCOM output
code. Table 2 provides a reference for the voltage. There are two methods for updating the
High-speed mode command code. (Note that this DAC/VCOM output voltages.
configuration is different from normal address
bytes—the low bit does not indicate read/write Method 1: Method 1 is used when it is desirable to
status.) The BUF08832 responds to the High-speed have the DAC/VCOM output voltage change
command regardless of the value of these last three immediately after writing to a DAC register. For each
bits. The BUF08832 does not acknowledge this byte; write transaction, the master sets data bit 15 to a '1'.
the communication protocol prohibits The DAC/VCOM output voltage update occurs after
acknowledgment of the Hs master code. Upon receiving the 16th data bit for the currently-written
receiving a master code, the BUF08832 switches on register.
its Hs mode filters, and communicates at up to Method 2: Method 2 is used when it is desirable to
3.4MHz. Additional high-speed transfers may be have all DAC/VCOM output voltages change at the
initiated without resending the Hs mode byte by same time. First, the master writes to the desired
generating a repeat START without a STOP. The DAC/VCOM channels with data bit 15 a '0'. Then,
BUF08832 switches out of Hs mode with the next when writing the last desired DAC/VCOM channel, the
STOP condition. master sets data bit 15 to a '1'. All DAC/VCOM
channels are updated at the same time after
GENERAL-CALL RESET AND POWER-UP receiving the 16th data bit.
The BUF08832 responds to a General-Call Reset,
which is an address byte of 00h (0000 0000) followed NONVOLATILE MEMORY
by a data byte of 06h (0000 0110). The BUF08832
acknowledges both bytes. Table 2 provides a BKSEL Pin
reference for the General-Call Reset command code. The BUF08832 has 16x rewrite capability of the
Upon receiving a General-Call Reset, the BUF08832 nonvolatile memory. Additionally, the BUF08832 has
performs a full internal reset, as though it had been the ability to store two distinct gamma curves in two
powered off and then on. It always acknowledges the different nonvolatile memory banks, each of which
General-Call address byte of 00h (0000 0000), but has 16x rewrite capability. One of the two available
does not acknowledge any General-Call data bytes banks is selected using the external input pin,
other than 06h (0000 0110). BKSEL. When this pin is low, BANK0 is selected;
When the BUF08832 powers up, it automatically when this pin is high, BANK1 is selected.
performs a reset. As part of the reset, the BUF08832
is configured for all outputs to change to the last
programmed nonvolatile memory values, or
1000000000 if the nonvolatile memory values have
not been programmed.

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 BUF08832

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When the BKSEL pin changes state, the BUF08832 Single-Channel Acquire Command
acquires the last programmed DAC/VCOM values from These are the steps to initiate a single-channel
the nonvolatile memory associated with this newly acquire:
chosen bank. At power-up, the state of the BKSEL
pin determines which memory bank is selected. 1. Be sure BKSEL is in its desired state and has
been stable for at least 1ms.
The I2C master also has the ability to update 2. Send a START condition on the bus.
(acquire) the DAC registers with the last programmed
nonvolatile memory values using software control. 3. Send the device address (based on A0) and
The bank to be acquired depends on the state of read/write bit = LOW. The BUF08832
BKSEL. acknowledges this byte.
4. Send a DAC/VCOM pointer address byte using the
General Acquire Command DAC/VCOM address corresponding to the output
and register to update with the OTP memory
A general acquire command is used to update all value. Set bit D7 = 0 and D6 = 1. Bits D5-D0 are
registers and DAC/VCOM outputs to the last the DAC/VCOM address. Although the BUF08832
programmed values stored in nonvolatile memory. A acknowledges 000000 through 010111, it stores
single-channel acquire command updates only the and returns data only from these addresses:
register and DAC/VCOM output of the DAC/VCOM
corresponding to the DAC/VCOM address used in the – 000000 through 000111
single-channel acquire command. – 010010
It returns 0000 reads from 001000 through
These are the steps of the sequence to initiate a 010001, and 010011 through 010111. See
general channel acquire: Table 4 for valid DAC/VCOM addresses.
1. Be sure BKSEL is in its desired state and has 5. Send a STOP condition on the bus.
been stable for at least 1ms.
2. Send a START condition on the bus. Approximately 36μs (±4μs) after issuing this
command, the specified DAC/VCOM register and
3. Send the appropriate device address (based on DAC/VCOM output voltage change to the appropriate
A0) and the read/write bit = LOW. The BUF08832 memory value.
acknowledges this byte.
4. Send a DAC/VCOM pointer address byte. Set bit MaxBank
D7 = 1 and D6 = 0. Bits D5-D0 are any valid
DAC/VCOM address. Although the BUF08832 The BUF08832 can provide the user with the number
acknowledges 000000 through 010111, it stores of times the nonvolatile memory of a particular
and returns data only from these addresses: DAC/VCOM channel nonvolatile memory has been
written to for the current memory bank. This
– 000000 through 000111 information is provided by reading the register at
– 010010 pointer address 111111.
It returns 0000 for reads from 001000 through
010001, and 010011 through 010111. See There are two ways to update the MaxBank register:
Table 4 for valid DAC/VCOM addresses. 1. After initiating a single acquire command, the
5. Send a STOP condition on the bus. BUF08832 updates the MaxBank register with a
code corresponding to how many times that
Approximately 750μs (±80μs) after issuing this particular channel memory has been written to.
command, all DAC/VCOM registers and DAC/VCOM 2. Following a general acquire command, the
output voltages change to the respective, appropriate BUF08832 updates the MaxBank register with a
nonvolatile memory values. code corresponding to the maximum number of
xxx times the most used channel (OUT1-8 and
VCOMs) has been written to.
xxx
MaxBank is a read-only register and is only updated
by performing a general- or single-channel acquire.

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Table 3 shows the relationship between the number READ/WRITE OPERATIONS

of times the nonvolatile memory has been
Read and write operations can be done for a single
programmed and the corresponding state of the
DAC/VCOM or for multiple DACs/VCOM. Writing to a
MaxBank Register.
DAC/VCOM register differs from writing to the
nonvolatile memory. Bits D15–D14 of the most
Table 3. MaxBank Details
significant byte of data determines if data are written
NUMBER OF TIMES WRITTEN TO RETURNS CODE to the DAC/VCOM register or the nonvolatile memory.
0 0000
1 0000 Read/Write: DAC/VCOM Register (volatile memory)
2 0001
The BUF08832 is able to read from a single
3 0010 DAC/VCOM, or multiple DACs/VCOM, or write to the
4 0011 register of a single DAC/VCOM, or multiple DACs/VCOM
5 0100 in a single communication transaction. DAC pointer
6 0101 addresses begin with 000000 (which corresponds to
7 0110 OUT1) through 000111 (which corresponds to
8 0111
OUT8). The VCOM address is 010010.
9 1000 Write commands are performed by setting the
10 1001 read/write bit LOW. Setting the read/write bit HIGH
11 1010 performs a read transaction.
12 1011
13 1100
Writing: DAC/VCOM Register (Volatile Memory)
14 1101 To write to a single DAC/VCOM register:
15 1110 1. Send a START condition on the bus.
16 1111
2. Send the device address and read/write bit =
LOW. The BUF08832 acknowledges this byte.
Parity Error Correction 3. Send a DAC/VCOM pointer address byte. Set bit
The BUF08832 provides single-bit parity error D7 = 0 and D6 = 0. Bits D5–D0 are the
correction for data stored in the nonvolatile memory DAC/VCOM address. Although the BUF08832
to provide increased reliability of the nonvolatile acknowledges 000000 through 010111, it stores
memory. If a single bit of nonvolatile memory for a and returns data only from these addresses:
channel fails, the BUF08832 corrects for it and – 000000 through 000111
updates the appropriate DAC with the intended value – 010010
when its memory is acquired. It returns 0000 for reads from 001000 through
If more than one bit of nonvolatile memory for a 010001, and 010011 through 010111. See
channel fails, the BUF08832 does not correct for it, Table 4 for valid DAC/VCOM addresses.
and updates the appropriate DAC/VCOM with the 4. Send two bytes of data for the specified register.
default value of 1000000000. Begin by sending the most significant byte first
(bits D15–D8, of which only bits D9 and D8 are
DIE_ID AND DIE_REV REGISTERS used, and bits D15–D14 must not be 01),
followed by the least significant byte (bits
The user can verify the presence of the BUF08832 in D7–D0). The register is updated after receiving
the system by reading from address 111101. The the second byte.
BUF08832 returns 0010001010000000 when read at
this address. 5. Send a STOP or START condition on the bus.

The user can also determine the die revision of the

BUF08832 by reading from register 111100.
BUF08832 returns 0000000000000000 when a RevA
die is present. RevB would be designated by
0000000000000001 and so on.

12 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

The BUF08832 acknowledges each data byte. If the 5. Send a STOP or START condition on the bus.
master terminates communication early by sending a
The BUF08832 acknowledges each byte. To
STOP or START condition on the bus, the specified
terminate communication, send a STOP or START
register is not updated. Updating the DAC/VCOM
condition on the bus. Only DAC registers that have
register is not the same as updating the DAC/VCOM
received both bytes of data are updated.
output voltage; see the Updating the DAC Output
Voltages section.
Reading: DAC/VCOM/OTHER Register (Volatile
The process of updating multiple DAC/VCOM registers Memory)
begins the same as when updating a single register. Reading a register returns the data stored in that
However, instead of sending a STOP condition after DAC/VCOM/OTHER register.
writing the addressed register, the master continues
to send data for the next register. The BUF08832 To read a single DAC/VCOM/OTHER register:
automatically and sequentially steps through 1. Send a START condition on the bus.
subsequent registers as additional data are sent. The
2. Send the device address and read/write bit =
process continues until all desired registers have
LOW. The BUF08832 acknowledges this byte.
been updated or a STOP or START condition is sent.
3. Send the DAC/VCOM/OTHER pointer address
To write to multiple DAC/VCOM registers: byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are
1. Send a START condition on the bus. the DAC/VCOM/OTHER address. NOTE: The
2. Send the device address and read/write bit = BUF08832 stores and returns data only from
LOW. The BUF08832 acknowledges this byte. these addresses:
3. Send either the OUT1 pointer address byte to – 000000 through 000111
start at the first DAC, or send the pointer address – 010010
byte for whichever DAC/VCOM is the first in the – 111100 through 111111
sequence of DACs/VCOM to be updated. The It returns 0000 for reads from 001000 through
BUF08832 begins with this DAC/VCOM and steps 010001, and 010011 through 010111. See
through subsequent DACs/VCOM in sequential Table 4 for valid DAC/VCOM/OTHER addresses.
order. 4. Send a START or STOP/START condition.
4. Send the bytes of data; begin by sending the 5. Send the correct device address and read/write
most significant byte (bits D15–D8, of which only bit = HIGH. The BUF08832 acknowledges this
bits D9 and D8 have meaning, and bits D15–D14 byte.
must not be 01), followed by the least significant
byte (bits D7–D0). The first two bytes are for the 6. Receive two bytes of data. They are for the
DAC/VCOM addressed in the previous step. The specified register. The most significant byte (bits
DAC/VCOM register is automatically updated after D15–D8) is received first; next is the least
receiving the second byte. The next two bytes are significant byte (bits D7–D0). In the case of
for the following DAC/VCOM. That DAC/VCOM DAC/VCOM channels, bits D15–D10 have no
register is updated after receiving the fourth byte. meaning.
This process continues until the registers of all 7. Acknowledge after receiving the first byte.
following DACs/VCOM have been updated. The 8. Send a STOP or START condition on the bus or
BUF08832 continues to accept data for a total of do not acknowledge the second byte to end the
18 DACs; however, the two data sets following read transaction.
the 16th data set are meaningless. The 19th data
set applies to VCOM. The 20th data set is
meaningless. The write disable bit cannot be
accessed using this method. It must be written to
using the write to a single DAC register
procedure.

Copyright © 2009–2011, Texas Instruments Incorporated 13

BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

Communication may be terminated by sending a To write to a single nonvolatile register:

premature STOP or START condition on the bus, or 1. Send a START condition on the bus.
by not acknowledging.
2. Send the device address and read/write bit =
To read multiple registers: LOW. The BUF08832 acknowledges this byte.
1. Send a START condition on the bus. Although the BUF08832 acknowledges 000000
through 010111, it stores and returns data only
2. Send the device address and read/write bit = from these addresses:
LOW. The BUF08832 acknowledges this byte.
– 000000 through 000111
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer address – 010010
byte for whichever register is the first in the It returns 0000 for reads from 001000 through
sequence of DACs/VCOM to be read. The 010001, and 010011 through 010111. See
BUF08832 begins with this DAC/VCOM and steps Table 4 for DAC/VCOM addresses.
through subsequent DACs/VCOM in sequential 3. Send a DAC/VCOM pointer address byte. Set bit
order. D7 = 0 and D6 = 0. Bits D5–D0 are the
4. Send a START or STOP/START condition on the DAC/VCOM address.
bus. 4. Send two bytes of data for the nonvolatile register
5. Send the correct device address and read/write of the specified DAC/VCOM. Begin by sending the
bit = HIGH. The BUF08832 acknowledges this most significant byte first (bits D15–D8, of which
byte. only bits D9 and D8 are data bits, and bits
D15–D14 must be 01), followed by the least
6. Receive two bytes of data. They are for the significant byte (bits D7–D0). The register is
specified DAC/VCOM. The first received byte is the updated after receiving the second byte.
most significant byte (bits D15–D8; only bits D9
and D8 have meaning), next is the least 5. Send a STOP condition on the bus.
significant byte (bits D7–D0). The BUF08832 acknowledges each data byte. If the
7. Acknowledge after receiving each byte of data. master terminates communication early by sending a
8. When all desired DACs have been read, send a STOP or START condition on the bus, the specified
STOP or START condition on the bus. nonvolatile register is not updated. Writing a
nonvolatile register also updates the DAC/VCOM
Communication may be terminated by sending a register and output voltage.
premature STOP or START condition on the bus, or
by not sending the acknowledge bit. The reading of The DAC/VCOM register and DAC/VCOM output voltage
registers DieID, DieRev, and MaxBank is not are updated immediately, while the programming of
supported in this mode of operation (these values the nonvolatile memory takes up to 250μs. Once a
must be read using the single register read method). nonvolatile register write command has been issued,
no communication with the BUF08832 should take
Write: Nonvolatile Memory for the DAC Register place for at least 250μs. Writing or reading over the
serial interface while the nonvolatile memory is being
The BUF08832 is able to write to the nonvolatile written jeopardizes the integrity of the data being
memory of a single DAC/VCOM in a single stored.
communication transaction. In contrast to the
BUF20820, writing to multiple nonvolatile memory Read: Nonvolatile Memory for the DAC Register
words in a single transaction is not supported. Valid
DAC/VCOM pointer addresses begin with 000000 To read the data present in nonvolatile register for a
(which corresponds to OUT1) through 000111 (which particular DAC/VCOM channel, the master must first
corresponds to OUT8). The VCOM address is 010010. issue a general acquire command, or a single acquire
command with the appropriate DAC/VCOM channel
When programming the nonvolatile memory, the chosen. This action updates both the DAC/VCOM
analog supply voltage must be between 9V and 20V. register(s) and DAC/VCOM output voltage(s). The
Write commands are performed by setting the master may then read from the appropriate
read/write bit LOW. DAC/VCOM register as described earlier.

14 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

Programmable VCOM Limits 1. If the VCOM OTP write is enabled, then the VCOM
input is always stored in the OTP. Limit
The BUF08832 VCOM output has a programmable
comparison happens only before the DAC output.
HIGH limit and LOW limit. The implementation and
interface of these limits are the same as with the 2. If the VCOM input is higher than the HIGH limit,
DAC registers. These registers are written to and then the HIGH limit is latched to the DAC output.
read back through the Two-Wire bus. Addresses for Reading of the DAC register returns the HIGH
limiters are 1E and 1F for the HIGH limit and LOW limit.
limit, respectively. See Table 4 for register pointer 3. If the VCOM input is lower than the LOW limit, then
addresses. the LOW limit is latched to the DAC output.
Reading of the DAC register returns the LOW
Upon power-up or general-call reset, the DAC
limit.
registers (channels 1 though 8 and VCOM) are set to
200 (default) that corresponds to mid-scale output for 4. If the VCOM input is in between the HIGH and
a 10-bit DAC. The HIGH and LOW limit registers are LOW limit, then the programmed value is latched
set to 3FF and 000 respectively. Therefore, the limits to DAC output. Reading of the DAC register
are transparent if not programmed. returns the programmed value.
5. If the HIGH limit is lower than the LOW limit, then
The BUF08832 uses double-buffered registers. The
the BUF08832 ignores the limits and latches the
input of data is stored in the first layer. The input may
programmed value to the DAC output. Reading of
be latched to the DAC output, depending upon
the DAC register returns the programmed value.
application. The DACs update only when the second
layer of latches are enabled. There are two banks of OTP associated with each of
the two limit registers. OTP operations on these two
The HIGH and LOW limits can be programmed to any
addresses are valid, just like OTP for DAC registers.
desired value to limit the VCOM output. The limit can
be programmed before or after programming the
VCOM channel. Because the input of data is stored in
the first layer of latches, the VCOM output is limited
according to the following rule in either sequence:

Table 4. DAC Register Pointer Addresses

DAC REGISTER POINTER ADDRESS
OUT1 000000
OUT2 000001
OUT3 000010
OUT4 000011
OUT5 000100
OUT6 000101
OUT7 000110
OUT8 000111
VCOM 010010
HIGH Limit 011110
LOW Limit 011111
OTHER REGISTER POINTER ADDRESS
Die_Rev 111100
Die_ID 111101
MaxBank 111111

Copyright © 2009–2011, Texas Instruments Incorporated 15

16
Write single DAC register. P4-P0 specify DAC address. Write Operation
Start Device Address Write Ackn DAC address pointer. D7-D5 must be 000. Ackn DAC MSbyte. D14 must be 0. Ackn DAC LSbyte Ackn Stop

SCL
BUF08832

SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

Device_Out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

If D15 = 1, all DACs are updated when the current DAC register is updated.

The entire DAC register D9-D0

is updated at this moment.
Write multiple DAC registers. P4-P0 specify DAC address. Write Operation
Start Device Address Write Ackn DAC address pointer. D7-D5 must be 000. Ackn DAC (pointer) MSbyte. D14 must be 0. Ackn DAC (pointer) LSbyte Ackn DAC (pointer + 1) MSbyte. D14 must be 0.

SCL

SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn D15 D14 D13

Device_Out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn D15 D14 D13

If D15 = 1, all DACs are updated when the current DAC register is updated.
SBOS476C – AUGUST 2009 – REVISED JULY 2011

The entire DAC register D9-D0

is updated at this moment.

DAC 20 (VCOM OUT2) MSbyte. D14 must be 0. Ackn DAC 20 LSbyte Ackn Stop

D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

Figure 15. Write DAC Register Timing

D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

Read single DAC register. P4-P0 specify DAC address. Read operation.

Start Device Address Write Ackn DAC address pointer. D7-D5 must be 000. Ackn Start Device Address Read Ackn DAC MSbyte. D15-D10 have no meaning. Ackn DAC LSbyte. No Ackn Stop

SCL

SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0

Device_Out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 No Ackn

Read multiple DAC registers. P4-P0 specify DAC address. Read operation.

Start Device Address Write Ackn Start DAC address pointer. D7-D5 must be 000. Ackn Start Device Address Read Ackn DAC (pointer) MSbyte. D15-D10 have no meaning. Ackn

SCL

SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn

Device_Out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn

DAC 20 (VCOM OUT2) MSbyte. D15-D10 have no meaning. Ackn DAC 20 LSbyte. Ackn Stop

D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

Figure 16. Read Register Timing

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Copyright © 2009–2011, Texas Instruments Incorporated

 www.ti.com

Write single OTP register. P4-P0 specify DAC address. Write operation.
Start Device Address Write Ackn DAC address pointer. D7-D0 must be 000. Ackn DAC MSbyte. D15-D14 must be 01. Ackn DAC LSbyte. Ackn Stop

SCL

SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

Device_Out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn

The OTP memory update begins at this time and

requires up to 250ms to complete.

Copyright © 2009–2011, Texas Instruments Incorporated

Figure 17. Write Nonvolatile Register Timing
General acquire command. P4-P0 must specify and valid DAC address. Write Operation
Start Device address. Write Ackn DAC address pointer. D7-D5 must be 100. Ackn Stop

SCL

SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn

Device_Out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn

Single channel acquire command. P4-P0 must specify and valid DAC address. Write Operation
Start Device address. Write Ackn DAC address pointer. D7-D5 must be 010. Ackn Stop

SCL

SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn

Device_Out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn

Figure 18. Acquire Operation Timing

SBOS476C – AUGUST 2009 – REVISED JULY 2011
BUF08832

17
18
BUF08832

General-Call Reset Command

Start Address Byte = 00h Ackn Address Byte = 06h Ackn

SCL

SDA
SBOS476C – AUGUST 2009 – REVISED JULY 2011

Device begins reset at arrow and is in reset until ACK clock pulse.
Then the device acquires memory, etc., as it does at power-up.

Figure 19. General-Call Reset Timing

High-Speed Command

Start Address Byte = 00001xxx (HS Master Code) No Ackn

SCL

SDA

Device enters high-speed mode at ACK clock pulse.

Device exits high-speed mode with stop condition.

Figure 20. High-Speed Mode Timing

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 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

END-USER SELECTED GAMMA CONTROL DYNAMIC GAMMA CONTROL

Because the BUF08832 has two banks of nonvolatile Dynamic gamma control is a technique used to
memory, it is well-suited for providing two levels of improve the picture quality in LCD television
gamma control by using the BKSEL pin, as shown in applications. This technique typically requires
Figure 21. When the state of the BKSEL pin changes, switching gamma curves between frames. Using the
the BUF08832 updates all nine programmable buffer BKSEL pin to switch between two gamma curves
outputs simultaneously after 750μs (±80μs). does not often provide good results because of the
750μs required to transfer the data from the
To update all nine programmable output voltages nonvolatile memory to the DAC register. However,
simultaneously via hardware, toggle the BKSEL pin to dynamic gamma control can still be accomplished by
switch between Gamma Curve 0 (stored in Bank0) storing two gamma curves in an external EEPROM
and Gamma Curve 1 (stored in Bank1). and writing directly to the DAC register (volatile).
All DAC/VCOM registers and output voltages are The double register input structure saves
updated simultaneously after approximately 750μs. programming time by allowing updated DAC values to
be pre-stored into the first register bank. Storage of
5V
this data can occur while a picture is still being
BUF08832 displayed. Because the data are only stored into the
BKSEL
first register bank, the DAC/VCOM output values
remain unchanged—the display is unaffected. At the
beginning or the end of a picture frame, the
OUT1
Switch DAC/VCOM outputs (and therefore, the gamma
voltages) can be quickly updated by writing a '1' in bit
15 of any DAC/VCOM register. For details on the
operation of the double register input structure, see
Change in the Updating the DAC Output Voltages section.
BANK1
BANK0

Output Voltages
To update all nine programmable output voltages
simultaneously via software, perform the following
actions:
OUT8
STEP 1: Write to registers 1–9 with bit 15 always '0'.
STEP 2: Write any DAC/VCOM register a second time
Two-Wire
with identical data. Make sure that bit 15 is set to '1'.
All DAC/VCOM channels are updated simultaneously
after receiving the last bit of data.

Figure 21. Gamma Control

Copyright © 2009–2011, Texas Instruments Incorporated 19

BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

OUTPUT PROTECTION exceeded. Protection against the high current flow

may be provided by placing current-limiting resistors
The BUF08832 output stages can safely source and in series with the output, as shown in Figure 13.
sink the current levels indicated in Figure 1 and Select a resistor value that restricts the current level
Figure 2. However, there are other modes where to the maximum rating for the particular pin.
precautions must be taken to prevent to the output
stages from being damaged by excessive current
VS
flow. The outputs (OUT1 through OUT8, and VCOM)
include ESD protection diodes, as shown in
Figure 22. Normally, these diodes do not conduct and ESD Current
BUF08832
are passive during typical device operation. Unusual Steering Diodes
operating conditions can occur where the diodes may
conduct, potentially subjecting them to high, even
damaging current levels. These conditions are most OUTX
likely to occur when a voltage applied to an output or
exceeds (VS) + 0.5V, or drops below GND – 0.5V. VCOM

One common scenario where this condition can occur

is when the output pin is connected to a sufficiently
large capacitor, and the BUF08832 power-supply
source (VS) is suddenly removed. Removing the
power-supply source allows the capacitor to
discharge through the current-steering diodes. The
energy released during the high current flow period Figure 22. Output Pins ESD Protection
causes the power dissipation limits of the diode to be Current-Steering Diodes

20 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

GENERAL POWERPAD DESIGN example thermal land pattern mechanical drawing

CONSIDERATIONS is attached to the end of this data sheet.
The BUF08832 is available in a thermally-enhanced 3. Additional vias may be placed anywhere along
PowerPAD package. This package is constructed the thermal plane outside of the thermal pad area
using a downset leadframe upon which the die is to help dissipate the heat generated by the
mounted; see Figure 23(a) and Figure 23(b). This BUF08832 IC. These additional vias may be
arrangement results in the lead frame being exposed larger than the 13-mil diameter vias directly under
as a thermal pad on the underside of the package; the thermal pad. They can be larger because
see Figure 23(c). This thermal pad has direct thermal they are not in the thermal pad area to be
contact with the die; thus, excellent thermal soldered; thus, wicking is not a problem.
performance is achieved by providing a good thermal 4. Connect all holes to the internal plane that is at
path away from the thermal pad. the same voltage potential as the GND pins.
The PowerPAD package allows for both assembly 5. When connecting these holes to the internal
and thermal management in one manufacturing plane, do not use the typical web or spoke via
operation. During the surface-mount solder operation connection methodology. Web connections have
(when the leads are being soldered), the thermal pad a high thermal resistance connection that is
must be soldered to a copper area underneath the useful for slowing the heat transfer during
package. Through the use of thermal paths within this soldering operations. This configuration makes
copper area, heat can be conducted away from the the soldering of vias that have plane connections
package into either a ground plane or other easier. In this application, however, low thermal
heat-dissipating device. Soldering the PowerPAD to resistance is desired for the most efficient heat
the printed circuit board (PCB) is always required, transfer. Therefore, the holes under the
even with applications that have low power BUF08832 PowerPAD package should make
dissipation. This technique provides the necessary their connection to the internal plane with a
thermal and mechanical connection between the lead complete connection around the entire
frame die pad and the PCB. circumference of the plated-through hole.
6. The top-side solder mask should leave the
The PowerPAD must be connected to the most terminals of the package and the thermal pad
negative supply voltage on the device, GNDA and area with its twelve holes exposed. The
GNDD. bottom-side solder mask should cover the holes
1. Prepare the PCB with a top-side etch pattern. of the thermal pad area. This masking prevents
There should be etching for the leads as well as solder from being pulled away from the thermal
etch for the thermal pad. pad area during the reflow process.
2. Place recommended holes in the area of the 7. Apply solder paste to the exposed thermal pad
thermal pad. Ideal thermal land size and thermal area and all of the IC terminals.
via patterns for the HTSSOP-20 PWP package 8. With these preparatory steps in place, simply
can be seen in the technical brief, PowerPAD place the BUF08832 IC in position and run the
Thermally-Enhanced Package (SLMA002), chip through the solder reflow operation as any
available for download at www.ti.com. These standard surface-mount component. This
holes should be 13 mils (0,33mm) in diameter. preparation results in a properly installed part.
Keep them small, so that solder wicking through
the holes is not a problem during reflow. An

Copyright © 2009–2011, Texas Instruments Incorporated 21

BUF08832

SBOS476C – AUGUST 2009 – REVISED JULY 2011 www.ti.com

DIE

Side View (a)

Thermal
Pad

DIE

End View (b)

Bottom View (c)

Figure 23. Views of Thermally-Enhanced PWP Package

For a given θJA (listed in the Electrical

Characteristics), the maximum power dissipation is 5.0
shown in Figure 24 and calculated by Equation 2: 4.5
Maximum Power Dissipation (W)

PD =
(TMAX - TA
qJA ) (2)
4.0
3.5
3.0
Where: 2.5

PD = maximum power dissipation (W) 2.0

1.5
TMAX = absolute maximum junction temperature
1.0
(+125°C)
0.5
TA = free-ambient air temperature (°C) 0
-40 -20 0 20 40 60 80 100
TA, Free-Air Temperature (°C)

Figure 24. Maximum Power Dissipation

vs Free-Air Temperature
(with PowerPAD soldered down)

22 Copyright © 2009–2011, Texas Instruments Incorporated

 BUF08832

www.ti.com SBOS476C – AUGUST 2009 – REVISED JULY 2011

REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision September, 2009 (B) to Revision C Page

• Corrected error in x-axis value for Figure 11 ........................................................................................................................ 6

Changes from Revision September 2009 (A) to Revision B Page

• Changed the typ and max specifications for the Analog Power Supply, Total Ananlog Supply Current and Over
Temperature parameters of the Electrical Characteristics table ........................................................................................... 3
• Added Figure 4 ..................................................................................................................................................................... 5
• Moved Figure 7 ..................................................................................................................................................................... 6

Copyright © 2009–2011, Texas Instruments Incorporated 23

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BUF08832AIPWPR ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 95 BUF08832

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BUF08832AIPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BUF08832AIPWPR HTSSOP PWP 20 2000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
PWP 20 HTSSOP - 1.2 mm max height
6.5 x 4.4, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224669/A

www.ti.com
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