ITER, SIKSHA ‘O’ ANUSANDHAN (Deemed to be University) Assignment
Computer Science Engineering, Computer
Branch Program B.Tech
Science and Information Technology
Course Name Computer Organization and Architecture Semester 4th
Course Code EET2211 Academic Year 2024-25/EVEN
Assignment-2 Topic- A Top-Level View of Computer
GP-1
Function and Interconnection, Cache Memory
Learning Level L1: Remembering L3: Applying L5: Evaluating
(LL) L2: Understanding L4: Analysing L6: Creating
Q’s Questions COs LL
1 Describe the three key concepts of the von Neumann architecture. CO3 L1
List and briefly define the possible states that define an instruction execution. (without
2 CO3 L1
interrupt).
Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of
two fields: the first byte contains the opcode and the remainder the immediate operand
or an operand address.
a. What is the maximum directly addressable memory capacity (in bytes)?
3 b. Discuss the impact on the system speed if the microprocessor bus has: CO3 L2
1. 32-bit local address bus and a 16-bit local data bus, or
2. 16-bit local address bus and a 16-bit local data bus.
c. How many bits are needed for the program counter and the instruction register?
Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16-
bit microprocessor. Assume that, on average, 20% of the operands and instructions are
4 32 bits long, 40% are 16 bits long, and 40% are only 8 bits long. Calculate the CO3 L2
improvement achieved when fetching instructions and operands with the 32-bit
microprocessor.
5 Explain the reasons for using a memory hierarchy. CO4 L1
6 How does the principle of locality relate to the use of multiple memory levels?
7 Explain how cache addressing plays an important role in cache design? CO4 L1
A cache memory unit with capacity of N words and block size of B words is to be
designed. If it is designed as direct mapped cache, the length of the TAG field is 10
8 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of CO4 L2
the TAG field is ______ bits.
[Gate CSE 2017(SET-1)]
An 8-way set associative cache of size 64 KB(1 KB=1024bytes) is used in a system
with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK
9 OFFSET. The number of bits in the TAG is ___________. CO4 L2
[Gate CSE 2023]
For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show the
following information, in hexadecimal format:
a. Tag, Line, and Word values for a direct-mapped cache, using the format of
Figure 4.10 (page no-161)
10 CO4 L2
b. Tag and Word values for an associative cache, using the format of Figure 4.12
(page no-163)
c. Tag, Set, and Word values for a two-way set-associative cache, using the format of
Figure 4.15 (page no-167)
Assignment 2 Topic: A Top-Level View of Date of Assignment 2: Date of Submission:
Computer Function and 24.03.2025 31.03.2025
Interconnection, Cache Memory
Note:
1. Assignment carries a weightage of 20 marks out of 100
2. Course outcome CO3 AND CO4 were covered.
Able to explain the concepts that underline the modern Computers evolution,
CO1
function, and Organization.
Able to identify the appropriate organization of a computer for achieving the best
CO2
performance.
Course CO3 Able to analyze and demonstrate the computer function and interconnection
Outcomes Able to understand and analyze the computer memory system.
CO4
CO5 Able to understand and analyze computer arithmetic via digital logic.
Able to interpret low level processor operations using a series of computer
CO6
instructions
