B.
Tech/CSE/CS301/ODD/R23/R / 1
Roll Number
Narula Institute of Technology
An Autonomous Institute under MAKAUT
2024
END SEMESTER EXAMINATION - ODD 2024
CS301 - COMPUTER ORGANIZATION AND ARCHITECTURE
TIME ALLOTTED: 3Hours FULL MARKS: 70
Instructions to the candidate:
Figures to the right indicate full marks.
Draw neat sketches and diagram wherever is necessary.
Candidates are required to give their answers in their own words as far as practicable
Group A
(Multiple Choice Type Questions)
Answer any ten from the following, choosing the correct alternative of each question: 10×1=10
1.i) The bulk of the binary information in a digital computer is stored in (1) CO3 BL2
memory, but all computations are done in
a) RAM
b) Memory Registers
c) Processor Registers
d) Secondary Memory.
1.ii) Associative memory is a (1) CO4 BL2
a) Pointer addressable memory
b) Content addressable memory
c) Very cheap memory
d) Slow memory
1.iii) The simplest way to determine cache locations in which to store (1) CO1 BL1
memory blocks is the,
a) Associative Mapping technique
b) Direct Mapping technique
c) Set-Associative Mapping technique
d) Indirect Mapping technique
1.iv) ..................................represents an organization that includes (1) CO4 BL2
many processing units under the supervision of a common control
unit.
a) SISD
b) SIMD
c) MISD
d) MIMD
1.v) Which of the following best describes the function of the ALU's (1) CO1 BL1
control signals?
a) They determine the data path within the memory.
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b) They select the operation to be performed by the ALU.
c) They manage power consumption in the CPU.
d) They store the results of operations.
1.vi) Which one of the following CPU registers holds the address of the (1) CO1 BL2
instructions (instructions in the program stored in memory) to be
executed next?
a) MAR (Memory address register)
b) MBR (Memory Buffer Register)
c) IR (Instruction Register)
d) PC (Program Counter).
1.vii) The simplest way to determine cache locations in which to store (1) CO3 BL2
memory blocks is the
a) Associative Mapping technique
b) Direct Mapping technique
c) Set-Associative Mapping technique
d) Indirect Mapping technique
1.viii) If the Main Memory, Cache memory size and block size are (1) CO2 BL4
128KB, 16KB and 256B respectively, then the no. of Tag bits in
PA if Direct mapping technique is used-
a) 8
b) 16
c) 3
d) 17
1.ix) A computer with cache memory access time of 200 ns, (1) CO4 BL2
mainmemory access time of 2000 ns and hit ratio of 0.9 produces
anaverage memory access time of
a) 250
b) 218
c) 190
d) 300
1.x) A machine has 24 bit instruction format. It has 32 registrers and (1) CO2 BL1
each of which is 32 bit long. It needs to support 49 instructions.
Each instruction has two reegister and one immidiate opperand. If
the immidiate opperand is signed integer, then what is the
minimum value of immidiate opprand.
a) 127
b) - 127
c) 128
d) - 128
e) 0
1.xi) What is a major drawback of pipelining? (1) CO3 BL1
a) Increased throughput
b) Pipeline hazards
c) Simplified control logic
d) Reduced latency
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1.xii) What is the purpose of virtual memory? (1) CO4 BL1
a) To increase the physical size of the RAM
b) To allow the execution of processes that require more memory than physically available
c) To speed up data access times
d) To store data permanently
Group B
(Short Answer Type Questions)
(Answer any three of the following) 3x5=15
2. We have 256 MB main memory and 1 MB Cache memory. The (5) CO5 BL3
address space of processor is 256 MB. The block size is 128 bytes.
Determine size fields in the address for Direct mapping and
Associative mapping cache schemes:
3. Answer each part (5)
a) What do you mean by Control Hazards (2) CO3 BL2
b) What are the solution methodology to deal with the control hazards (3) CO3 BL2
4. Consider a fully associative cache with 8 cache blocks (0-7). The (5) CO3 BL3
memory block requests are in the order-4, 3, 25, 8, 19, 6, 25, 8, 16,
35, 45, 22, 8, 3, 16, 25, 7. If LRU replacement policy is used, which
cache block will have memory block 7? Also, calculate the hit ratio.
5. Compare between RISC and CISC architecture (5) CO2 BL4
6. Answer each part (5)
a) Represent -7.5 in IEEE 754 single-precision format (2) CO2 BL3
b) What value is represented by IEEE single precision floating point (3) CO2 BL3
number
0 10000011 010100000000000000000000
Group C
(Long Answer Type Questions)
(Answer any three of the following) 3x15=45
7. Answer each part (15)
a) Differentiate between multiprocessor and multicomputer. (5) CO4 BL4
b) Differentiate between NUMA and COMA Architecture. (5) CO4 BL4
c) Draw and explain suffle exchange network interconnection network (5) CO4 BL4
8. Answer each parts (15)
a) Write the addressing modes in brief (5) CO2 BL2
b) Represent -7.5 in IEEE 754 single-precision format. (3) CO2 BL4
c) In a sample machine with load store architecture having clock rate (7) CO1 BL4
50 MHz. Let the instruction frequency be as for a program-
Operation Frequency No of clock cycle
ALU 40 1
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Load 20 2
Store 10 2
Branch 30 2
calculate the MIPS of the machine.
9. Answer each parts (15)
a) What do you mean by CPI ? What is the value of CPI for a RISC (4) CO1 BL2
processor?
b) In a sample machine with load store architecture having clock rate (6) CO1 BL4
50 MHz. Let the instruction frequency be as for a program-
Operation Frequency No of clock cycle
ALU 40 1
Load 20 2
Store 10 2
Branch 30 2
Calculate the MIPS of the machine.
c) Compare between RISC and CISC architecture. (5) CO4 BL4
10. i. Describe the key performance metrics used to evaluate (15) CO1 BL1
computer systems, including throughput, latency, and
utilization.
ii. Discuss how benchmarks are used to assess performance and
the importance of choosing appropriate benchmarks.
iii. Analyze the impact of architectural decisions (e.g., pipelining,
cache design) on overall system performance.
11. Answer each parts (15)
a) Explain properties of memory hierarchy (5) CO3 BL2
b) A hiearachical cache- main memory subsystem has the following (5) CO3 BL4
specification:
i) Cache access time of 50 nsec
ii) main memory access time 500 nsec
iii) 80% of memory request are for read
iv) hit ratio of 0.9 for read access and the write through scheme is
used.
calculate
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a) average access time of the memory system considering only
memory read cycle.
b) average access time of the system both for read and write
requests.
c) How many RAM chips are required to design a large RAM memory- (5) CO3 BL5
type of size 1Kx8 using same size smaller RAM chips each of size
256x4? Draw the block diagram the connection of this lager RAM
with CPU of specification 16-address bus and 8 data bus
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