DATE:
Design, simulation and synthesis of Adders
EXP:1
AIM:
To design, simulate and synthesis of different adders.
SOFTWARE REQUIRED:
Cadence Incisive Tool.
Cadence Genus Tool.
PROCEDURE:
STEP 1: Right-click on the RedHat window, select "Open Terminal", and create a project
folder using mkdir project_name && cd project_name.
STEP 2: Then open the design file using gedit project_name.v, write the Verilog code, and
save it.
STEP 3: Then create and open the testbench file using gedit project_name _tb.v, enter the
testbench code, and save it.
STEP 4: Start the Cadence tool by running csh and launching NCLaunch using nclaunch -
new.
STEP 5: Inside NCLaunch, click Multistep → Library → Create cds.lib, save the file, and
compile the Verilog design and testbench files.
STEP 6: Select the testbench from worklib, elaborate it, and move to the snapshot section.
STEP 7: Open the waveform viewer, right-click on the testbench, select Simulation and Run,
and observe the waveform.
STEP 8: Right-click on the testbench file again, choose Schematic Tracer, and generate the
circuit representation.
STEP 10: Create a synthesis folder using mkdir logic_synthesis && cd logic_synthesis,
then move the design, testbench, constraints, and synthesis script into it.
STEP 11: Open Genus Synthesis Tool by running genus, then execute synthesis by typing
source rcscript.tcl to generate the netlist, timing, power, and area reports.
STEP 12: Analyse the generated reports, document the results, and verify the final netlist for
correctness.
HALF
ADDER:
PROGRAM:
module halfadd(s,c,a,b);
output s,c;
input a,b;
assign s=a^b;
assign c= a&b;
endmodule
TEST BENCH:
module halfadder_tb;
wire s,c;
reg a,b;
halfadd g1(s,c,a,b);
initial
begin
a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10 $stop;
end
endmodule
OUTPUT :
SYNTHESIS REPORT:
AREA REPORT
POWER REPORT
NETLIST REPORT
FULL ADDER
PROGRAM:
module fulladder
( input a,b,cin,
output sum,carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (cin & a) ;
endmodule
TEST BENCH:
module fulladder_tb;
reg a,b,cin;
wire sum,carry;
fulladder uut(a,b,cin,sum,carry);
initial begin
a = 0; b = 0; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 0;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 0;
#10 a = 1; b = 1; cin = 1;
#10 $finish();
end
endmodule
OUTPUT :
SYNTHESIS REPORT:
AREA REPORT :
POWER REPORT:
NETLIST REPORT :
RIPPLE CARRY ADDER:
module
rca( input
[3:0]a,b, input
cin,
output [3:0]sum,
output c4);
wire c1,c2,c3;
full_adder fa0(a[0],b[0],cin,sum[0],c1);
full_adder fa1(a[1],b[1],c1,sum[1],c2);
full_adder fa2(a[2],b[2],c2,sum[2],c3);
full_adder fa3(a[3],b[3],c3,sum[3],c4);
endmodule
module
full_adder( input
a,b,cin, output
sum,carry);
assign sum = a ^ b ^ cin;
assign carry = (a & b)|(b & cin)|(cin & a);
endmodule
OUTPUT:
SYNTHESIS REPORT:
AREA REPORT :
POWER REPORT:
NETLIST REPORT:
RESULT:
Thus, the design, simulation, and synthesis of adders were done by Cadence tool.
