EXP.
NO:02 ESTIMATION OF POWER IN ADDERS
DATE:22/08/2025
AIM:
To simulate Ripple Carry Adder and Carry Look Ahead Adder and also to obtain
power consumption and utilization report for analysis.
SOFTWARE USED:
Xilinx Vivado
PROCEDURE:
1. Open Xilinx virtuoso Tool
2. Create a new project and Add source for writing the source code. Write the
Verilog HDL code for creating a ripple carry adder and carry look ahead adder by
following the step-by-step procedure given in manual document.
3. Perform simulation and verify the functionality of the circuit.
4.Synthesize the code and obtain the utilization and power report of the adders and
tabulate.
SIMULATION:
CONSTRAINTS:
CODE
A: RIPPLE CARRY ADDER
`timescale 1ns/1ps
module full_adder (
input A, B, Cin,
output Sum, Cout
);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (Cin & A);
endmodule
module rca2_comb (
input [1:0] A, B,
input Cin,
output [1:0] Sum,
output Cout
);
wire c1;
full_adder FA0 (.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(c1));
full_adder FA1 (.A(A[1]), .B(B[1]), .Cin(c1), .Sum(Sum[1]), .Cout(Cout));
endmodule
module rca2_top (
input clk,
input [1:0] A, B,
input Cin,
output reg [1:0] Sum,
output reg Cout
);
wire [1:0] sum_int;
wire cout_int;
rca2_comb RCA (.A(A), .B(B), .Cin(Cin), .Sum(sum_int), .Cout(cout_int));
always @(posedge clk) begin
Sum <= sum_int;
Cout <= cout_int;
end
endmodule
SCHEMATIC:
POWER REPORT:
TESTBENCH:
`timescale 1ns/1ps
module tb_rca2_top;
reg clk;
reg [1:0] A, B;
reg Cin;
wire [1:0] Sum;
wire Cout;
rca2_top dut (.clk(clk), .A(A), .B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout));
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
Cin=0; A=2'b00; B=2'b00; #20;
Cin=0; A=2'b01; B=2'b01; #20;
Cin=0; A=2'b10; B=2'b11; #20;
Cin=1; A=2'b11; B=2'b01; #20;
Cin=0; A=2'b11; B=2'b11; #20;
$finish;
end
endmodule
TIMING REPORT:
ILA:
SYNTHESIS REPORT TABLE:
B: CARRY LOOKAHEAD ADDER
SIMULATION
CODE:
B: CARRY LOOKAHEAD ADDER
`timescale 1ns/1ps
module cla2_comb (
input [1:0] A, B,
input Cin,
output [1:0] Sum,
output Cout
);
wire [1:0] G, P;
wire [2:0] C;
assign C[0] = Cin;
assign G = A & B;
assign P = A ^ B;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & C[1]);
assign Sum = P ^ C[1:0];
assign Cout = C[2];
endmodule
module cla2_top (
input clk,
input [1:0] A, B,
input Cin,
output reg [1:0] Sum,
output reg Cout
);
wire [1:0] sum_int;
wire cout_int;
cla2_comb CLA (.A(A), .B(B), .Cin(Cin), .Sum(sum_int), .Cout(cout_int));
always @(posedge clk) begin
Sum <= sum_int;
Cout <= cout_int;
end
endmodule
SCHEMATIC:
CONSTRAINTS:
TESTBENCH:
`timescale 1ns/1ps
module tb_cla2_top;
reg clk;
reg [1:0] A, B;
reg Cin;
wire [1:0] Sum;
wire Cout;
cla2_top dut (.clk(clk), .A(A), .B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout));
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
Cin=0; A=2'b00; B=2'b00; #20;
Cin=0; A=2'b01; B=2'b01; #20;
Cin=1; A=2'b10; B=2'b01; #20;
Cin=0; A=2'b11; B=2'b01; #20;
Cin=1; A=2'b11; B=2'b11; #20;
$finish;
end
endmodule
SYNTHESIS REPORT TABLE:
POWER REPORT:
ILA:
IMPLEMENTED DEVICE:
POWER CONSUMPTION WITH AND WITHOUT CLOCK GATING:
SNO. DESIGN POWER STATIC POWER DYNAMIC
CONSUMED POWER
1 RIPPLE CARRY 11.478W 1.042W 10.437
ADDER
2 CARRY LOOK AHEAD 11.104W 1.040W 10.064
ADDER
RESULT:
Thus the Ripple Carry Adder and Carry Look Ahead Adder are simulated,
functionality is verified, and power consumption and utilization report for analysis are
also obtained.
