SYSTEM DESIGN LAB

(21ECP612)

SUBMITTED BY:
JATIN KATIYAR
(2024PEV5264)

UNDER THE SUPERVISION OF:

Dr. AMIT JOSHI

AY 2024-25
ELECTRONICS & COMMUNICATION ENGINEERING
DEPARTMENT
MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY
JAIPUR, INDIA

pg. 1
 INDEX

Exp. Experiment Date Remark/Sign

No.
1 To design and simulate basic logic gates.

2 To design and simulate Half adder and Full

Adder.

3 To design and simulate half subtractor and

full subtractor.

4 To design and simulate 2:1 multiplexer.

5 To design and simulate 1:2 Demux

6 To design and simulate SR Flipflop

7 To design and simulate JK Flipflop

8 To design and simulate T Flipflop

9 To design and simulate full adder using virtual

input and output.

10 Implementation of input logic analyzer

pg. 2
 Experiment 1 : Basic Logic Gate

Aim :
To design and simulate basic logic gates.

Tools used:
AMD Vivado

Truth table:

Verilog codes Testbench->

`timescale 1ns / 1ps

`timescale 1ns / 1ps
module test_bench;
module logic_gates( reg a, b;
input a, b, wire and_g,
output and_g, or_g,
output or_g, not_g,
output not_g, nand_g,
output nand_g, nor_g,
output nor_g, xor_g,
output xor_g, xnor_g;
output xnor_g
);
logic_gates dut(a, b,
assign and_g = a&b;
and_g,or_g,not_g,nand_g,nor_g,xor
assign or_g = a|b;
assign not_g = ~a; _g,xnor_g);
assign nand_g = ~(a&b); initial begin
#10 a= 1'b0; b= 1'b0;
assign nor_g = ~(a|b);
#10 a= 1'b0; b= 1'b1;
assign xor_g = a^b;
assign xnor_g = ~(a^b); #10 a= 1'b1; b= 1'b0;
endmodule #10 a= 1'b1; b= 1'b1;
end
endmodule

pg. 3
 RTL block

Simulations:

pg. 4
 Experiment 2 : Half Adder and Full Adder

Aim :
To design and simulate Half adder and Full Adder.

Tools used:
AMD Vivado

Truth table:

Half Adder

Full Adder

Verilog codes
`timescale 1ns / 1ps
`timescale 1ns / 1ps module test_bench_ha;
reg a, b;
module half_adder( wire sout, cout;
input a, b, reg clk;

half_adder dut(a, b, sout, cout);

output sout, cout always #5 clk = ~clk;
); initial begin
clk = 0;
a = 0; b = 0;
assign sout = a^b;
#10; a = 0; b = 1;
assign cout = a&b; #10; a = 1; b = 0;
#10; a = 1; b = 1;
endmodule #10; $finish;
end
always @(posedge clk) begin
$display("a = %b, b = %b, sum = %b, carry = %b",
a,b, sout, cout);end endmodule
pg. 5
 `timescale 1ns / 1ps
`timescale 1ns / 1ps module test_bench;
reg a, b, cin;
module full_adder( wire sout, cout;
input a, b, cin, reg clk;
output sout, cout full_adder dut(a, b, cin, sout, cout);
); always #5 clk = ~clk;
initial begin
assign sout = a ^ clk = 0; a = 0; b = 0; cin = 0;
b ^ cin; #10; a = 0; b = 0; cin = 1;
assign cout = #10; a = 0; b = 1; cin = 0;
(a&b) | cin&(a^b); #10; a = 0; b = 1; cin = 1;
endmodule #10; a = 1; b = 0; cin = 0;
#10;a = 1; b = 0; cin = 1;
#10;a = 1; b = 1; cin = 0;
#10;a = 1; b = 1; cin = 1;
#10; $finish;
end
always @(posedge clk) begin
$display("a = %b, b = %b, cin = %b, sum = %b,
carry = %b", a, b, cin, sout, cout);
end
endmodule

RTL block

Full Adder

Half Adder

pg. 6
 Simulations:

Full Adder Half Adder

pg. 7
 Experiment 3 : Half Subtractor and Full Subtractor

Aim :
To design and simulate half subtractor and full subtractor.

Tools used:
AMD Vivado

Truth table:

Half Subtractor

Full Subtractor

Verilog codes

`timescale 1ns / 1ps `timescale 1ns / 1ps

module test_bench_hs;
module half_subtractor( reg a, b;
input a, b, wire diff, bout;
output diff, bout reg clk;
); half_subtractor dut(a, b, diff, bout);
always #5 clk = ~clk;
assign diff = a ^ b; initial begin
assign bout = ~a & b; clk = 0; a = 0; b = 0;
#10; a = 0; b = 1;
endmodule #10; a = 1; b = 0;
#10; a = 1; b = 1;
#10 $finish;
end
always @(posedge clk) begin
$display("a: %b, b: %b, difference: %b, borrow:
%b", a, b, diff, bout);
end
endmodule

pg. 8
 `timescale 1ns / 1ps
module test_bench_fs;
`timescale 1ns / 1ps reg a, b, bin;
module full_subtractor( wire diff, bout;
input a, b, bin, reg clk'
output diff, bout); full_subtractor dut(a, b, bin, diff, bout);
assign diff = a ^ b ^ bin; always #5 clk = ~clk;
assign bout = (~a & (b^bin)) | (b initial begin
& bin) ; clk = 0; a = 0; b = 0; bin = 0;
endmodule #10; a = 0; b = 0; bin = 1;
#10; a = 0; b = 1; bin = 0;
#10; a = 0; b = 1; bin = 1;
#10; a = 1; b = 0; bin = 0;
#10; a = 1; b = 0; bin = 1;
#10; a = 1; b = 1; bin = 0;
#10; a = 1; b = 1; bin = 1;
#10; $finish;
end
always @(posedge clk) begin
$display("a: %b, b: %b, bin: %b, difference:
%b, borrow: %b", a, b, bin, diff, bout);
end
endmodule

RTL block

Full subtractor Half Subtractor

Simulations:

Full Subtractor Half Subtractor

pg. 9
 Experiment 4 : 2:1 Multiplexer (MUX)

Aim :
To design and simulate 2:1 multiplexer.

Tools used:
AMD Vivado

Truth table:

Verilog codes
`timescale 1ns / 1ps

module mux_2_1(
input [1:0] i,
input select,
output y_out );
assign y_out= select ? i[1] :
i[0];
endmodule

`timescale 1ns / 1ps

module test_bench;
reg [1:0] i;
reg select;
wire y_out;
mux_2_1 dut(i, select, y_out);
always begin
i=$random;
select=$random;
#10;
end
initial
begin $monitor("Input Data : %0d
Select Line : %0d Output : %0d ",i,
select, y_out);
#100 $finish;
end
endmodule

pg. 10
 RTL block

Simulations:

pg. 11
 Experiment 5 : 1:2 Demultiplexer (DEMUX)

Aim:
To design and simulate 1:2 demux .

Tools used
AMD Vivado

Truth table

Verilog code
`timescale 1ns / 1ps
`timescale 1ns / 1ps module test_bench;
reg sel, i;
module demux_1_2( wire [1:0]y;
input sel, demux_1_2 dut(sel, i, y);
input i, initial begin
output y0, y1 sel=0; i=0;
); #10;sel=0; i=1;
assign {y0,y1} = #10;sel=1; i=0;
sel?{1'b0,i}: {i,1'b0}; #10;sel=1; i=1;
endmodule end
initial
begin
$monitor("sel: %b i: %b y[0]: %b
y[1]: %b", sel, i, y[0], y[1]);
#40 $finish; end
endmodule
RTL block

pg. 12
 Simulation

pg. 13
 Experiment 6 : SR Flip Flop
Aim :
To design and simulate SR Flipflop

Tools used:
AMD Vivado

Truth table:

Verilog codes module sr_ff_tb();

module sr_ff(S,R,clk,Q,Qbar); reg S,R,clk;
input S,R,clk; wire Q,Qbar;
output Q,Qbar; sr_ff uut(.S(S),.R(R),.Q(Q),.clk(clk),.Qbar(Qbar));
reg Q;
initial
always @(posedge clk)
begin clk=1'b0;
Q<=0; always
case({S,R}) #5 clk=~clk;
2'b00:Q<=Q; initial begin
2'b01:Q<=0;
2'b10:Q<=1;
S=1'b0;R=1'b0;#100;
2'b11:Q<=1'bx; S=1'b0;R=1'b1;#100;
default: Q<=0; S=1'b1;R=1'b0;#100;
endcase S=1'b1;R=1'b1;#100;
end $finish;
assign Qbar=~Q;
endmodule
end
endmodule
Simulations:
RTL block

pg. 14
 Experiment 7 : JK Flip Flop
Aim :
To design and simulate JK Flipflop

Tools used:
AMD Vivado

Truth table:

Verilog codes
`timescale 1ns / 1ps
module test_bench;
reg clk,rst,j,k;
`timescale 1ns / 1ps wire Q;
JK_flipflop dut(j,k,clk,rst,Q);
module JK_flipflop( initial begin
input j,k,clk,reset, clk=0;
output reg Q forever #5 clk=~clk;
); end
always@(posedge clk) initial
begin begin
if({reset}) rst=1;
Q <= 1'b0; #10;
else j = 1'b0;
begin k = 1'b0;
case({j,k}) #10;
2'b00:Q<=Q; rst=0;
2'b01:Q<=1'b0; #10;
2'b10:Q<=1'b1; j = 1'b0;
2'b11:Q<=~Q; k = 1'b1;
endcase #10;
end j = 1'b1;
end k = 1'b0;
endmodule #10;
j = 1'b1;
k = 1'b1;
#10;
end
initial begin
$monitor("\t clk: %d J: %d K: %d Q:
%d", clk, j, k, Q);
#80 $finish;
end
endmodule

pg. 15
 RTL block

Simulations:

pg. 16
 Experiment 8 : T Flip Flop
Aim :
To design and simulate T FlipFlop.

Tools used:
AMD Vivado

Truth tabl e:

Verilog codes

`timescale 1ns / 1ps `timescale 1ns / 1ps

module test_bench;
module T_flipflop( reg clk,rst,t;
input t,clk,reset, wire q;
output reg Q T_flipflop dut(t,clk,rst,q);
); initial
always@(posedge clk) begin
begin clk=0;
if(reset) t=0;
Q <= 1'b0; forever #4 clk=~clk;
else end
begin initial
if(t) begin
Q<= ~Q; rst=1;
else #10;
Q<= Q; rst=0;
end forever
end begin
endmodule #10 t = 1'b1;
#20 t = 1'b0;
end
end
initial begin
$monitor("\t clock: %b T: %b
Q: %b",clk,t,q);
#100$finish;
end
endmodule

pg. 17
 RTL block

Simulations:

pg. 18
 Experiment 9 : VIO
(virtual input and output)

Aim :
To design and simulate full adder using virtual input and output.

Tools used:
AMD Vivado

Verilog codes
`timescale 1ns / 1ps
module lab1( input [3:0] din,
input [3:0] din1,
output [3:0] dout, output cout
);
assign {cout,dout} = din+din1;
endmodule

RTL block

VIO integration with adder block

pg. 19
 HDL Code for clock

pg. 20
 Experiment 10 : ILA
(input logic analyzer)
Aim :
Implementation of Input logic analyzer

Tools Used
AMD Vivado

RTL block

pg. 21
 Integrated VIO and ILA with adder

pg. 22