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​ ​
Module 3
26. Write a program to evaluate the arithmetic statement ​
​ ​ Y=(A+B)*(C+D)​​ ​ ​
Using a general register computer with three address instructions.
​ Using a general register computer with two address instructions.
​ Using an accumulator type computer with one address instructions.
​ Using a stack organized computer with zero-address operation instruction.
​ [Module3/CO1/Apply-HOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 10
27. Explain Implied and Immediate Addressing mode with suitable examples.
​ [Module3/CO1/Understand-LOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
28.Explain Autoincrement and Stack Addressing mode with suitable examples.​
​ [Module3/CO1/Understand-LOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
29.Explain Register Direct and Register Indirect Addressing mode with suitable examples.
​ [Module3/CO1/Apply-IOCQ] ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
30. Evaluate the following arithmetic statement using two address instructions and one address
instructions.
​ X= (M+N) *(P+Q) ​​ ​
​ [Module3/CO1/Apply-IOCQ] ​​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
Module 4
31. Show the bus connection with a CPU to connect four RAM chips of size 128×8 bits each and a
ROM chip of 512×8 bit size. Assume the CPU has 8-bit data bus and 16-bit address bus. Clearly
specify generation of chip select signals. ​
​ [Module4/CO3/Apply-HOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 10
32. Show the bus connection with a CPU to connect four RAM chips of size 256×8 bits each and a
​ ROM chip of 1024×8 bit size. Assume the CPU has 8-bit data bus and 16-bit address bus. ​
Clearly specify generation of chip select signals. ​
​ [Module4/CO3/Apply-HOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 10
33. Explain the concept of Paging and describe Page Faults in detail. ​
[Module4/CO3/ understand-IOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ 3+2
34. How does cache memory enhance the performance of a computer?
​ Explain the concept of hit ratio.
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35. Assume that for a certain processor, a read request takes 50ns on a cache miss and 5ns on a
cache hit. Suppose while running a program, it was observed that 80% of the processors read
requests result in a cache hit. Find the average ​ read access time.​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ [Module4/CO3/ Apply-HOCQ] ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 4
36. A computer has a main memory of 64K×16 and a cache memory of 1K words. ​ The cache
uses
direct mapping with a block size of four words.
​ (i)​ How many bits are there in the tag, block and word fields of the address format?
​ (ii)How many bits are there in each word of cache?
​ (iii)How many blocks can the cache accommodate?
​ [Module4/CO3/ Apply-HOCQ] ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 6
37. Describe the memory hierarchy pyramid and explain the relationship between cost, speed,
and capacity.​ ​ ​ ​ ​ ​
​ [Module4/CO3/Understand-LOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
38. Differentiate between static RAM and Dynamic RAM.
​ [Module4/CO3/ Analyze-IOCQ] ​​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
39. Differentiate ‘write through’ and ‘write back’ policies in cache memory? ​
[Module4/CO3/ Analyze-IOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5 40. Explain the role of virtual memory
in computer systems. ​ ​ ​ ​ ​ ​ ​
[Module4/CO3/ Understand-IOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
41. Differentiate between logical address space and physical address space and explain how
they are related?​ ​ ​ ​ ​ ​ ​
[Module4/CO3/Understand-IOCQ] ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
42.Explain in brief ‘Content Addressable Memory’.
[Module4/CO3/Understand-IOCQ]​​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5
43. Compare paging and segmentation methods.​ ​
[Module4/CO3/ Analyze-IOCQ] ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7
44. Explain the concept of locality of reference in computer memory systems.
[Module4/CO3/Understand-IOCQ] ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 4
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45. For a given 256MB main memory and 1 MB cache memory, determine the size of the
subfields (in bits) in the address for direct mapping, associative and set associative mapping
cache schemes. ​ ​ ​
​ The address space of this processor is 256 MB.
​ The block size is 128 bytes.
​ There are 8 blocks in a cache set.​ ​
​ [Module4/CO3/ Apply-HOCQ] ​​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 8
46. Determine the number of bits required for the tag field in a 4-way set associative cache
memory unit with a capacity of 16KB, a block size of 8 words, ​ and a word length of 32 bits,
given that the physical address space is 4GB. ​
[Module 4/CO3/Apply-HOCQ]​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​
​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 8

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