EE141-Fall 2008
Digital Integrated
Circuits
Domino Logic
Lecture 21
Domino Logic
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Announcements Domino Logic
Project phase 2 out today, due next
Fri.
Clk Mp Clk Mp Mkp
1→1
Out1 Out2
1→0
0→0
In1 0→1
In2 PDN In4 PDN
In3 In5
Clk Me Clk Me
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Class Material Why Named Domino?
Last lecture
Dynamic logic Clk
Today’s lecture
Domino logic Ini PDN Ini PDN Ini PDN Ini PDN
Inj Inj Inj Inj
Reading
Clk
Chapter 7
Like falling dominos!
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Properties of Domino Logic Buffer “Average” LE
Only non-inverting logic can be implemented
Very high speed
static inverter can be skewed, only L-H transition
critical
Input capacitance reduced – smaller logical effort
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Domino Logic LE Optimal EF/stage with Domino
Domino buffers are faster than static
CMOS inverters
Is optimal EF/stage for a chain of domino
gates still 4?
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Domino Logic LE (skewed static gate) Designing with Domino Logic
VDD VDD
VDD
Clk Mp Clk Mp Mr
Out2
Out1
In1
In2 PDN In4 PDN
In3
Can be eliminated
Clk Me Clk Me
Inputs = 0
during precharge
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Footless Domino Differential (Dual Rail) Domino
VDD VDD VDD
Clk Mp Mkp Mkp Mp Clk
Clk Mp Clk Mp Clk Mp Out = AB Out = AB
Out1 Out2 Outn
0 1 0 1 0 1 A
In1 In2 In3 Inn !A !B
1 0 1 0 1 0 1 0 B
Clk Me
The first gate in the chain needs a foot switch
Precharge is rippling – short-circuit current
Allows inverting gates to be built
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Footless Domino np-CMOS
Clk Mp Clk Me
1→1
Out1
1→0
In1 In4 PUN
In2 PDN In5
0→0
In3 0→1
Out2
Mp
(to PDN)
Can mitigate short-circuit current by alternating between footed Clk Me Clk
and unfooted domino
Only 0 → 1 transitions allowed at inputs of PDN
Only 1 → 0 transitions allowed at inputs of PUN
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Footless Domino NORA Logic
VDD VDD VDD
Clk Mp Clk Me
1→1
Out1
Clk Mp Clk Mp Clk Mp
1→0
Out1 Out2 Outn In4 PUN
In1
0 1 0 1 0 1 In5
In2 PDN
In1 In2 In3 Inn
0→0
1 0 1 0 1 0 1 0
In3 0→1
Out2
Mp
(to PDN)
Clk Me Clk
To eliminate the short-circuit current, can delay the clock for
each stage
Fast, but EXTREMELY sensitive to noise!
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Next Lecture
Flops and Latches
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