Madan Mohan Malaviya Univ.

of Technology, Gorakhpur

VLSI Design (BEC-41)

(Unit-2, Lecture-1)

Presented By:
Prof. R. K. Chauhan
Department of Electronics and Communication Engineering
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Fabrication Process Flow:

Basic Steps

Fig. Process steps required for patterning of silicon dioxide.

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Fabrication Process Flow:

Basic Steps

Fig. Process steps required for patterning of silicon dioxide (continued).

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Fabrication of the nMOS

Transistor

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Fabrication of the nMOS

Transistor

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Fabrication of the nMOS

Transistor

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Fabrication of the nMOS

Transistor

• The surface is covered

with evaporated
aluminum which will
form the
interconnects (Fig. k).
• Finally, the metal layer
is patterned and
etched, completing
the interconnection of
the MOS transistors
on the surface (Fig. L).

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The CMOS n-Well Process

• The n-well CMOS process starts with a moderately doped (with
impurity concentration typically less than 1015 cm-3) p-type silicon
substrate.
• Then, an initial oxide layer is grown on the entire surface.
• The first lithographic mask defines the n-well region.
• Donor atoms, usually phosphorus, are implanted through this window
in the oxide.

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The CMOS n-Well

Process

Fig. Basic steps of the LOCOS process to

create oxide isolation around active areas.

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The CMOS n-Well

Process Fig. The creation of the n-well region,
a thick field oxide is grown in the
areas surrounding the transistor's
active regions, and a thin gate oxide is
grown on top of the active regions.
The thickness and the quality of the
gate oxide are two of the most
critical fabrication parameters, since
they strongly affect the operational
characteristics of the MOS transistor,
as well as its long-term reliability.

Fig. The polysilicon layer is

deposited using chemical vapor
deposition (CVD) and patterned by
dry (plasma) etching. The created
polysilicon lines will function as the
gate electrodes of the nMOS and the
pMOS transistors and their
interconnects.
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The CMOS n-Well

Process
Fig. Using a set of two masks, the n+
and p+ regions are implanted into
the substrate and into the n-well,
respectively. Also, the ohmic contacts
to the substrate and to the n-well
are implanted in this process step.

Fig. An insulating silicon dioxide

layer is deposited over the entire
wafer using CVD. Then, the contacts
are defined and etched away to
expose the silicon or polysilicon
contact windows. These contact
windows are necessary to complete
the circuit interconnections using
the metal layer, which is patterned in
the next step.

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The CMOS n-Well

Process Fig. Metal (aluminum) is deposited
over the entire chip surface using
metal evaporation, and the metal
lines are patterned through
etching. Since the wafer surface is
non- planar, the quality and the
integrity of the metal lines created
in this step are very critical and are
ultimately essential for circuit
reliability.

Fig. The composite layout and the

resulting cross-sectional view of
the chip, showing one nMOS and
one pMOS transistor (in the n-well),
and the polysilicon and metal
interconnections. The final step is
to deposit the passivation layer (for
protection) over the chip, except
over wire-bonding pad areas.

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VLSI Design (BEC-41)

(Unit-2, Lecture-2)

Presented By:
Prof. R. K. Chauhan
Department of Electronics and Communication Engineering
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MOS
• INVERTER
Inverter is fundamental logic gate uses single input.
• Basic principles employing in design and analysis of inverter can be
directly applied on complex gates.
• Therefore, inverter design forms basis for digital circuits.
• First we start with DC Characteristics. The DC response is Ultra Low
Frequency response of the Circuit.
• When you are at a logic low or high before switching, it is a DC condition.
• The transient can be thought of as a perturbation of the DC Since valid
logic levels are a range of voltages, it is a tolerant system.

Fig. Voltage transfer

characteristic (VTC) of the ideal
inverter

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Noise Immunity and Noise

Margins

• Output signal is transmitted through interconnect to next inverter.

• Interconnects are prone to noise. Suppose output of 1st inverter is
perturbed to a level higher than VIL. Then this can not predict correct
output of 2nd inverter.
• Thus, VIL is maximum allowable input voltage which is low enough
to ensure ‘1’ output.
• Similarly argument for VIH.
• Noise tolerance or Noise Margins and denoted by NM. Two noise margins
will be defined for low signal level as NML and high signal level as NMH

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Noise Immunity and Noise

Margins

NML = VIL - VOL

NMH = VOH -VIH

• Noise tolerance or Noise

Margins and denoted by NM.
• Two noise margins will be
defined for low signal level as
NML and high signal level as
NMH

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Noise Immunity and Noise

•
Margins
If the input signal is perturbed from its nominal value because of
external influences, such as noise:

Perturbed Output = Nominal Output + Gain x External Perturbation

• If the magnitude of the voltage gain at the nominal input voltage Vin is
smaller than unity, then the input perturbation is not amplified and,
consequently, the output perturbation remains relatively small.
• Otherwise, with the voltage gain larger than unity, a small perturbation in
the input voltage level will cause a rather large perturbation in the output
voltage.
• Hence, we define the boundaries of the valid input signal regions as the
voltage points where the magnitude of the inverter voltage gain is equal
to unity.
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Noise Immunity and Noise

Margins
Critical Parameters for Inverter design:

VOH: Maximum output voltage when the output level is logic " 1"
VOL: Minimum output voltage when the output level is logic "0"
VIL: Maximum input voltage which can be interpreted as logic "0"
VIH: Minimum input voltage which can be interpreted as logic "
1"

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Power and Area

•
Consideration
The DC power dissipation of an inverter is defined as

PDC = VDD. IDC

• Current depends upon input and output voltage levels. Assume
input voltage level 50% is at logic ‘0’ and 50% at logic ‘1’.

• To reduce chip area, one has to reduce the size of transistor i.e. gate
area (W x L). Thus keep W/L ratio close to unity.

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Inverters with different

types of load
1. Resistive-Load Inverter

2. Depletion-load NMOS Inverter

3. Enhancement-load NMOS Inverter

4. CMOS Inverter

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Resistive-Load
Inverter • The average DC power consumption of the
resistive-load inverter circuit is found by
considering two cases, Vin = VOL (Low) and
Vin = VOH (high).
• When the input voltage is equal to VOL, the
driver transistor is in cut-off. Consequently,
there is no steady-state current flow in the
circuit (ID = IR = 0), and the DC power
dissipation is equal to zero.
• When the input voltage is equal to VOW on
the other hand, both the driver MOSFET
and the load resistor conduct a nonzero
current. Since the output voltage in this
case is equal to VOL'
• The current drawn from the power
supply can be found as:

• The chip area occupied by the resistive-load inverter circuit depends on two parameters,
the (W/L) ratio of the driver transistor and the value of the resistor RL. The area of the
driver transistor can be approximated by the gate area, (WxL).
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Resistive-Load
Inverter
Table: Operating regions of the driver transistor in
the resistive-load inverter.

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Resistive-Load
Inverter

Fig. Typical VTC of a resistive-load

inverter circuit.

Fig. Voltage transfer characteristics of the resistive-

load inverter, for different value of the parameter (kn,
RL )
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Depletion-load NMOS
Inverter • Several disadvantages of the enhancement-
type load inverter can be avoided by using a
depletion-type nMOS transistor as the load
device.-
• The fabrication process for producing an
inverter with an enhancement-type nMOS
driver and a depletion-type nMOS load is
slightly more complicated and requires
additional processing steps, especially for
the channel implant to adjust the threshold
voltage of the load device.

• The resulting improvement of circuit performance and integration possibilities, however,

easily justify the additional processing effort required for the fabrication of depletion-load
inverters.

• The immediate advantages of implementing this circuit configuration are:

(i) Sharp VTC transition and better noise margins,
(ii) single power supply, and
(iii) smaller overall layout area.
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Depletion-load NMOS
Inverter

Fig.(a) Inverter circuit with saturated enhancement-type nMOS load. (b) Inverter with linear enhancement-type
load.

• The circuit configurations of two inverters with enhancement-type load devices

are depending on the bias voltage applied to its gate terminal, the load transistor
can be operated either in the saturation region or in the linear region.
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Depletion-load NMOS Inverter

(Continued..)
• Both types of inverters have some distinct advantages and disadvantages from
the circuit design point of view.
• The saturated enhancement-load inverter shown in Fig.(a) requires a single voltage
supply and a relatively simple fabrication process, yet the VOH level is limited to (VDD –
VTIoad)
• The load device of the inverter circuit shown in Fig. (b), on the other hand, is always
biased in the linear region. Thus, the VOH level is equal to VDD, resulting in higher
noise margins compared to saturated enhancement-load inverter.
• The most significant drawback of this configuration is the use of two separate
power supply voltages.
• In addition, both types of inverter circuits suffer from relatively high stand-by
(DC) power dissipation
• Hence, enhancement-load nMOS inverters are not used in any large-scale digital
applications.

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CMOS
Inverter
• The CMOS inverter has two important advantages over the other
inverter configurations:
• The first and perhaps the most important advantage is that the steady-
state power dissipation of the CMOS inverter circuit is virtually negligible,
except for small power dissipation due to leakage currents. In all other
inverter structures examined so far, a nonzero steady-state current is
drawn from the power source when the driver transistor is turned on, which
results in a significant DC power consumption.
• The other advantages of the CMOS configuration are that the voltage
transfer characteristic (VTC) exhibits a full output voltage swing between 0
V and VDD, and that the VTC transition is usually very sharp. Thus, the VTC
of the CMOS inverter resembles that of an ideal inverter.

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CMOS
Inverter

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CMOS
A: P Linear N Cut-off
Inverter B: P Linear N Saturation
C: P saturation N Saturation
D: P Saturation N Linear
E: P Cut-off N Linear

For Symmetric Inverter:

VT0=VT0n=-VT0p and KR=1

Fig. VTC Characteristic

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VLSI Design (BEC-41)

(Unit-2, Lecture-3)

Presented By:
Prof. R. K. Chauhan
Department of Electronics and Communication Engineering
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Resistive-Load
Inverter

Table: Operating regions of the driver transistor in

the resistive-load inverter.

Fig. Resistive load inverter

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Resistive-Load
Inverter

Fig. Typical VTC of a resistive-load

inverter circuit. Important design
parameters of the circuit are shown
in the inset.

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Resistive-Load
Inverter
Calculation of VOH
• First, we note that the output voltage Vout is given
by

• When the input voltage Vin is low, i.e., smaller than the threshold
voltage of the driver MOSFET, the driver transistor is cut-off.
• Since the drain current of the driver transistor is equal to the load
current,
IR= ID = 0.
• It follows that the output voltage of the inverter under these conditions
is:

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Resistive-Load
Inverter
Calculation of VOL
• To calculate the output low voltage VOL, we assume that the input voltage is
equal to VOH i.e., Vin = VOH = VDD. Since Vin – VT0 > VOUT in this case, the driver
transistor operates in the linear region. Also note that the load current IR is:

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Resistive-Load
Inverter
Calculation of VIL
• By definition, VIL is the smaller of the two input voltage values at which
the slope of the VTC becomes equal to (-1),i.e., dVout/ dVin = - 1.
• Simple inspection of VTC that when the input is equal to VIL, the
output voltage (Vout) is only slightly smaller than VOH.
• Consequently, Vout> Vin- VT0, and the driver transistor operates in saturation.

• To satisfy the derivative condition, we differentiate both sides of equation

with respect to Vin, which results in the following equation:

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Resistive-Load
Inverter
Calculation of VIH
• VIH is the larger of the two voltage points on VTC at which the slope is equal
to (-1).
• When the input voltage is equal to VIH, the output voltage Vout, is only
slightly larger than the output low voltage VOL.
• Hence, Vout< Vin-VT0, and the driver transistor operates in the linear region.

• Differentiating both sides with respect to Vin, we

obtain:

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Resistive-Load
Inverter
Calculation of VIH (Continued..)
• Next, we can substitute dVout /dVin = - 1 into previous equation, since the
slope of the VTC is equal to (-1) also at Vin= VIH

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Resistive-Load
Inverter

Fig. Voltage transfer characteristics of the resistive-load inverter, for different values of the parameter
(kn,RL)
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VLSI Design (BEC-41)

(Unit-2, Lecture-4)

Department of Electronics and Communication Engineering

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CMOS
Inverter
• The CMOS inverter has two important advantages over the other
inverter configurations:
• The first and perhaps the most important advantage is that the steady-
state power dissipation of the CMOS inverter circuit is virtually negligible,
except for small power dissipation due to leakage currents. In all other
inverter structures examined so far, a nonzero steady-state current is
drawn from the power source when the driver transistor is turned on, which
results in a significant DC power consumption.
• The other advantages of the CMOS configuration are that the voltage
transfer characteristic (VTC) exhibits a full output voltage swing between 0
V and VDD, and that the VTC transition is usually very sharp. Thus, the VTC
of the CMOS inverter resembles that of an ideal inverter.

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CMOS
Inverter

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CMOS
Inverter

Fig. Operating regions of the nMOS and the pMOS transistors.

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CMOS
Inverter

• In Region A, where Vin< VT0, the NMOS transistor is cut-off and the
output voltage is equal to VOH =VDD.
• As the input voltage is increased beyond VT0,n, (into Region B), the
NMOS transistor starts conducting in saturation mode and the
output voltage begins to decrease. Also note that the critical voltage
VIL which corresponds to (dVout/dVin) =-1 is located within Region B.

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CMOS
Inverter
• As the output voltage further decreases, the PMOS transistor enters
saturation at the boundary of Region C. It is seen from figure that
the inverter threshold voltage, where Vin= Vout, is located in Region C.
• When the output voltage Vout, falls below (Vin – VT0,n), the NMOS
transistor starts to operate in linear mode. This corresponds to Region
D in figure, where the critical voltage point VIH with (dVout/dVjn) = -1 is
also located.
• Finally, in Region E, with the input voltage Vin > (VDD + VT0,p), the PMOS
transistor is cut-off, and the output voltage is VOL= 0.
• It has already been established that VOH = VDD and VOL = 0 for this
inverter; thus, we will devote our attention to VIL, VIH and the
inverter switching threshold, Vth.

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CMOS
Inverter
Calculation of VIL
• By definition, the slope of the VTC is equal to (-1), i.e., dVout/dVin = -1
when the input voltage is Vin = VIL.
• Note that in this case, the NMOS transistor operates in saturation
while the PMOS transistor operates in the linear region.
• From ID,n= ID,p , we obtain the following current equation:

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CMOS
Inverter
Calculation of VIL
• To satisfy the derivative condition at VIL , we differentiate both sides
with respect to Vin.

• Substituting Vin = VIL and (dVout / dVin) = -1 in above equation, we obtain:

where kR is defined as:

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CMOS
Inverter
Calculation of VIH
• When the input voltage is equal to VIH, the NMOS transistor operates in
the linear region, and the PMOS transistor operates in saturation.
Applying KCL to the output node, we obtain

• Now, differentiate both sides with respect to

Vin:

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CMOS
Inverter
Calculation of VIH
• Substituting, Vin = VIH and (dVout/ dVin) =-1 in above equation, we
obtain

• Again, this equation must be solved simultaneously with the KCL

equation to obtain the numerical values of VIH and Vout.

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CMOS
Inverter
Calculation of Vth
• The inverter threshold voltage is defined as Vth = Vth = Vout, Since the CMOS
inverter exhibits large noise margins and a very sharp VTC transition, the
inverter threshold voltage emerges as an important parameter
characterizing the DC performance of the inverter.
• For Vin= Vout, both transistors are expected to be in saturation mode;
hence, we can write the following KCL equation:

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CMOS
Inverter
Calculation of Vth
• The correct solution for Vin for this equation
is:

• Finally, the inverter threshold (switching threshold) voltage Vth, is found

as

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CMOS
Inverter
Calculation of Vth

Fig. Typical VTC and the

power supply current of
a CMOS inverter circuit.

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CMOS
Inverter
Calculation of Vth
• Now solve for kR that is required to achieve the given Vth:

• Recall that the switching threshold voltage of an ideal inverter is defined

as:

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CMOS
Inverter
Calculation of Vth
• For a near-ideal CMOS VTC that satisfies the above condition. Since the
operations of the NMOS and the PMOS transistors of the CMOS inverter
are fully complementary, we can achieve completely symmetric input-
output characteristics by setting the threshold voltages as VT0 = VT0,p =
|VT0,p|. This reduces to:

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CMOS
Inverter

Fig. Voltage transfer

characteristics of three CMOS
inverters, with different
NMOS- to-PMOS ratios.

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VLSI Design (BEC-41)

(Unit-2, Lecture-5)

Department of Electronics and Communication Engineering

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Switching Characteristics of
CMOS Inverter

Fig. Input and output voltage waveforms of a

typical inverter, and the definitions of propagation
delay times.

• The propagation delay times ᵅ PHL and ᵅ PLH are found from Figure as

ᵅ PHL = t1- t0 and ᵅ PLH = t3- t2

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Switching Characteristics of CMOS

Inverter
• The propagation delay times ᵅ PHL and ᵅ PLH determine the input-to-output
signal delay during the high-to-low and low-to-high transitions of the output,
respectively.
• By definition, ᵅ PHL is the time delay between the V50%-transition of the
rising input voltage and the V50% -transition of the falling output voltage.
• Similarly, ᵅ PLH is defined as the time delay between the V50% -transition of
the falling input voltage and the V50% -transition of the rising output
voltage.

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Calculation of Delay Times

• The propagation delay times can be found more accurately by solving the
state equation of the output node in the time domain. The differential
equation associated with the output node is given below. Note that the
capacitance current is also a function of the output voltage.

Fig. Equivalent circuit of the CMOS inverter during

high-to-low output transition.

Fig. Input and output voltage waveforms

during high-to-low transition.
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Calculation of Delay Times

• First, consider the NMOS transistor operating in
saturation.

• the solution equation in the time interval between to and t1’ , can be found
as

• Evaluating this simple integral

yields

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Calculation of Delay Times

• At t = t1', the output voltage will be equal to (VDD – VT,n) and the transistor
will be at the saturation-linear region boundary.
• Next, consider the NMOS transistor operating in the linear region:

• The solution of equation in the time interval between t1' and t1 can be found
as

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Calculation of Delay
Times

• Finally, the propagation delay time for high-to-low output transition (TPHL)
can be found by combining both timing equations:

• For VOH = VDD and VOL= 0, as is the case for the CMOS inverter, becomes:

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Calculation of Delay Times

(Continued..)
• In a CMOS inverter, the charge-up event of the output load capacitance for
falling input transition is completely analogous to the charge-down event
for rising input.
• When the input voltage switches from high (VOH) to low (VOL), the NMOS
transistor is cut off, and the load capacitance is being charged up
through the PMOS transistor.
• Following a very similar derivation procedure, the propagation delay time
ᵅ PLH can be found as:

• For VOH = VDD and VOL = 0, equation becomes

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Calculation of Delay Times

(Continued..)
• In the following figure, the
falling- output propagation delay
ᵅ PHL (obtained from SPICE
simulation) is plotted as a
function of the NMOS channel
width.

• In fact, the increase in silicon area

can be viewed as a design trade-off
for delay reduction, since the circuit
speed improvements are typically
obtained at the expense of
increased transistor dimensions.

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Power Dissipation of CMOS Inverters

• There are two types of power dissipation in CMOS circuits: dynamic and
static:
Static power dissipation
Due to conduction of following currents:
• Subthreshold current
• Reverse biased PN-junction current
• Tunneling current
Dynamic power dissipation
• Due to charging and discharging of load capacitance
• Due to short circuit current

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Static power dissipation

Subthreshold current
Even though a transistor is logically turned off,
there is a non-zero leakage current through
the channel at the microscopic level, as
illustrated in Figure. This current is known as
the subthreshold leakage because it occurs
when the gate voltage is below its threshold
voltage.

Reverse biased PN-junction current

PN-junctions are formed at the source or drain
of transistors because of a parasitic effect of
the bulk CMOS device structure. The junction
current at the source or drain of the transistor
is picked up through the bulk or well contact.
The magnitude of the current depends on the
temperature, process, bias voltage and the area
of the PN-junction.
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Static power dissipation

Tunneling current
For MOSFETs with heavily doped channels
and ultrathin oxide layers, the field in the
oxide can reach very high values of MV/cm.
The ultrathin oxide layer reduces the width of
the energy barrier that separates the gate
from the channel, thus making it easier for
electrons/ holes to tunnel through the
insulator layer as shown in Figure.

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Dynamic power dissipation

Short circuit current

• CMOS inverter operating at VDD with the transistor threshold voltages of Vtn
and Vtp as marked on the transfer curve.
• When the input signal level is above Vtn the NMOS is turned on.
• Similarly, when the signal level is below Vtp the PMOS is turned on.
• When the input signal Vi switches, there is a short duration in which the
input level is between Vtn and Vtp and both transistors are turned on.
• This causes a short-circuit current from VDD to ground and dissipates power.

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Dynamic power dissipation

Charging and discharging of load capacitance

• The most significant source of dynamic power dissipation in CMOS
circuits is the charging and discharging of capacitance.
• Sometimes, capacitors are intentionally fabricated to achieve certain non-
digital operations such as charge sharing and signal delay.
• However, most digital CMOS circuits do not require capacitors for
their intended operations.
• The capacitance forms due to parasitic effects of interconnection wires
and transistors. Such
• parasitic capacitance cannot be avoided and it has a significant impact
on the power dissipation of the circuits.

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Dynamic power dissipation

Charging and discharging of load capacitance (Continued..)

• During the charging cycle from time t0 to t1 the energy

Es
drawn from the voltage source is

• Initially the capacitor contains no charge and the

voltage across its terminals is zero, i.e., Vc(to) =0.
Assume that the capacitor is fully charged at the end
of the charging cycle, we have Vc (t1) =V.

• Part of the electrical energy Es drawn from the voltage source is stored in the
capacitor and the rest is dissipated as heat energy in the resistor Re. The energy
Ecap stored in the capacitor at the end of the charging cycle is:
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Dynamic power dissipation

Charging and discharging of load capacitance (Continued..)

The energy Ec dissipated at Rc during charging is therefore

• Now consider the discharging cycle from t1 to t2, we assume that the
capacitor is fully discharged, i.e., Vc(t1) = V and Vc(t2) = 0. The energy Ed
dissipated in the discharge resistor Rd is

• Ed is exactly equal to the energy stored in the capacitance at the beginning of the
discharging cycle. If we charge and discharge the capacitance at the frequency of f
cycles per seconds, the power dissipation of the system is

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VLSI Design (BEC-41)

(Unit-2, Lecture-6)

Department of Electronics and Communication Engineering

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MOS Combinational
Circuit
• Combinational logic
circuits, or gates, which
perform Boolean
operations on multiple
input variables and
determine the outputs as
Boolean functions of the
inputs, are the basic
building blocks of all digital
systems.
• In this chapter, we will
examine the static and
dynamic characteristics of
various combinational MOS
logic circuits.
Fig. Generic combinational logic circuit (gate).

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MOS Combinational
Circuit • The output voltage of the
CMOS NOR2 (Two-Input NOR) Gate
CMOS NOR gate will attain a
logic-low voltage of VOL= 0
and a logic-high voltage of
VOH= VDD.
• For circuit design purposes,
the switching threshold
voltage Vth of the CMOS gate
emerges as an important
design criterion.
• We start our analysis of the
switching threshold by
assuming that both input
Fig. (Two-Input NOR) Gate. voltages switch
simultaneously, i.e., VA = VB.

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MOS Combinational
Circuit
CMOS NOR2 (Two-Input NOR) Gate
• The switching threshold by assuming that both input voltages
switch simultaneously, i.e., VA = VB.

• we can easily derive simple

design guidelines for the NOR2
gate. For example, in order to
achieve a switching threshold
voltage of VDD/2 for
simultaneous switching, we
have to set VT,n = |VTP| and k p= 4
kn.
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MOS Combinational
Circuit
CMOS NAND2 (2-Input NAND) Gate

• This figure shows the CMOS NOR2

gate with the parasitic device
capacitances, the inverter
equivalent, and the corresponding
lumped output load capacitance.
• In the worst case, the total
lumped load capacitance is
assumed to be equal to the sum
of all internal parasitic device
capacitances seen in Figure.

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MOS Combinational
Circuit
Complementary CMOS

• The complementary CMOS circuit style falls under a broad class of logic
circuits called static circuits in which at every point in time (except
during the switching transients), each gate output is connected to
either VDD or VSS via a low-resistance path.
• Also, the outputs of the gates assume at all times the value of the
Boolean function implemented by the circuit (ignoring, once again, the
transient effects during switching periods).
• A static CMOS gate is a combination of two networks, called the pull-up
network (PUN) and the pull-down network(PDN). The figure shows a
generic N input logic gate where all inputs are distributed to both the
pull- up and pull-down networks.

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MOS Combinational
Circuit
Complementary CMOS

Fig. Complementary logic gate as a combination of a PUN (pull-up network) and a PDN
(pull-down network)
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MOS Combinational
Circuit

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MOS Combinational
Circuit
Ratioed Logic

• Ratioed logic is an attempt to reduce the number of transistors required

to implement a given logic function, at the cost of reduced robustness
and extra power dissipation.
• The purpose of the PUN in complementary CMOS is to provide a conditional
path between VDD and the output when the PDN is turned off.
• In ratioed logic, the entire PUN is replaced with a single unconditional load
device that pulls up the output for a high output.
• Instead of a combination of active pull-down and pull-up networks, such a
gate consists of an NMOS pull-down network that realizes the logic
function, and a simple load device.

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MOS Combinational
Circuit
Ratioed Logic

Fig. Ratioed logic gate.

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MOS Combinational
Circuit
Ratioed Logic

Fig.. Four-input pseudo-NMOS NOR and NAND gates

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MOS Combinational
Circuit
DCVSL logic gate
• To create a ratioed logic style that completely eliminates static currents
and provides rail-to-rail swing. Such a gate combines two concepts:
differential logic and positive feedback.
• A differential gate requires that each input is provided in
complementary format, and produces complementary outputs in turn.
• The feedback mechanism ensures that the load device is turned off
when not needed. Example of such a logic family, called Differential
Cascode Voltage Switch Logic (or DCVSL).

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Problem 1: Design following Boolean expression using complementary

CMOS and Pseudo NMOS logic:
ᵄ = ᵃᵃ + ᵃ (ᵃ + ᵃ ) ᵄ = ᵃᵃ + ᵃᵃ + ᵃ .

Fig. using complementary CMOS logic Fig. using Pseudo NMOS logic
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Problem 2: Realized following Boolean function and find (W/L)n

equivalent and (W/L)p equivalent, if (W/L)n=10 and (W/L)p=15:
ᵄ = (ᵆ + ᵆ + ᵃ )(ᵆ + ᵆ)

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Problem 2:

A. Identify the worst-case input combination(s) for VOL.

B. Calculate the worst-case value of VOL. (Assume that all pull-down
transistors have the same body bias and initially, that VOL =5% VDD.)

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Solution
2: Class1: A-C
Class1: B-D
Class1: B-E
Class2: B-D-E
Class3: A-C-B-D-E
VOL1>VOL2>VOL3
Hence worst case VOL in class 1 combination.
Given: Rn/(Ru+Rn). VDD =5%VDD =VDD/20
Hence 19Rn= Ru
For Class1: VOL= 2Rn/(Ru+2Rn). VDD
VOL= VDD/10.5
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Problem 3: Find the effective output node capacitance in both two

cases of given figure:
A.The input VA is equal to VOH and the other input V is switching from VOH to
VOL.
B. VB is equal to VOH and VA switches from VOH to VOL.

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Solution
•3:The input VA is equal to VOH and the other input V is switching from VOH to VOL.
In this case, both the output voltage VOUT, and the internal node voltage Vx will
rise, resulting in:

• Note that this value is quite conservative and fully reflects the internal node
capacitances into the lumped output capacitance Cload in reality, only a
fraction of the internal node capacitance is reflected into Cload.
• Now consider another case where VB is equal to VOH and VA switches from
VOH to VOL. In this case, the output voltage Vout, will rise, but the internal node
voltage Vx, will remain low because the bottom driver transistor is on. Thus,
the lumped output capacitance is

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