Accredited by NBA & NAAC with "A" Grade Recognized by UGC under section 2(f) & 12(B) Approved

byAICTE
-New Delhi Permanently Affiliated to JNTUK,SBTET Ranked as "A" Grade by Govt.o

Internship Report On
VERY LARGE SCALE INTEGRATION

By
MUTYA PAVAN PHANI SAI VISWESWARA SANDEEP

(22K61A1435)
Bachelor of Engineering

In

Electronics and Communication Technology

APLMS-SKILLDZIRE

FROM

(May to June 2024)

(8 Weeks)

0
1
DEPARTMENT OF ELECTRONICS & COMMUNICATION TECHNOLOGY

CERTIFICATE
This is to certify that the internship work entitled “VERY LARGE SCALE
INTEGRATION ”, APLMS-SKILLDZIRE (03-05-2024 to 03-07-2024)” is being
submitted by MUTYA PAVAN PHANI SAI VISWESWARA
SANDEEP(22K61A1435) in partial fulfillment for the award of Degree of

BACHELOR OF TECHNOLOGY in ELECTRONICS & COMMUNICATION

TECHNOLOGY to the Jawaharlal Nehru Technological University, Kakinada during

the academic year 2024-25 is a record of bonafide work carried out by them under our
supervision.

INTERNSHIP COORDINATOR: HEAD OF THE

DEPARTMENT MR.N.SUBBARAYUDU DR.P.N.MALLESWARI

2
 ACKNOWLEDGEMENT

I take immense pleasure to express my deep sense of gratitude to our beloved Mr.N.Subbarayudu,
internship coordinator for his valuable suggestions and rare insights ,constant encouragement, and
inspiration throughout the internship work.
I express my deep sense of gratitude to our beloved Principal, Dr. Mohammed Ismail, for his
valuable guidance and for permitting us to carry out this internship.
I express my deep sense of gratitude to Dr. P.N. Malleswari, Head of the Department for the valuable
guidance and suggestions, keen interest shown and thorough encouragement extended throughout the period
of internship work.
I am grateful to my internship coordinator and thanks to all teaching and nonteaching staff members
who contributed for the successful completion of our internship work.

With Gratitude
MUTYA PAVAN PHANI SAI VISWESWARA SANDEEP
22K61A1435

3
 DECLARATION

I MUTYA PAVAN PHANI SAI VISWESWRA SANDEEP, registration number 22K61A1435, student Of
Electronics and Communication Technology at Sasi Institute of Technology & Engineering, Tadepalligudem
hereby declare that the Summer Training Report entitled “APLMS-SKILLDZIRE”is an authentic
record of my own work as requirements of Industrial Training during the period from 01/05/24 to 30 /06/24. I
obtained the knowledge of industry recognized cybersecurity and network security concepts as well as various
cutting-edge advancements across all Palo Alto Networks technologies. through the selfless efforts of the
Employee arranged to me by the Organisation. A Training Report was made on the same and the suggestions
given by the faculty were duly incorporated.

M.P.P.S.V. SANDEEP
22K61A1435

4
 Vision of the Institute:
Aspire to be a leading institute in professional education by creating technocrats to propel
societal transformations through inventions and innovations.

Mission of the Institute:

1. To impart technology integrated active learning environments that nurtures technical & life
skills.

2. To enhance scientific temper through active research leading to innovations & sustainable
environment.

3. To create responsible citizens with highest ethical standards.

Vision of the Program:

To equip students with technical expertise needed to make a significant contribution in emerging
trends that propel societal transformation in Electronics and Communication Technologies.

Mission of the Program:

1. To provide a dynamic learning environment that equips students with the technical expertise
required to make meaningful contributions in the field of Electronics and Communication
Technologies.

2. To nurture critical thinking, foster creativity and teamwork that prepare graduates to meet
the industry needs.

3. To inculcate among students a sense of integrity and highest level of professionalism fortified
with ethical values.

Program Educational Objectives

PEO1: Apply knowledge gained to comprehend engineering principles in the field of Electronics
and
Communication Technology.

PEO2: Able to pursue higher education and excel in research to provide solutions in
emerging technological trends.

5
PEO3: To apply life long learning to solve societal problems with the highest level of intensification.

Program Specific Outcomes

PSO1. Able to provide innovative solutions to engineering challenges in the realms of

communication, signal processing, VLSI, and embedded systems.

PSO.2 Graduates will able to mathematically model, simulate and develop prototypes using
modern simulators.

PROGRAM OUTCOMES

PO1 Engineering Knowledge PO6 Engineer & Society PO11 Project Mgt. & Finance

PO2 Problem Analysis PO7 Environment & PO12 Life Long Learning
Sustainability

PO3 Design & Development PO8 Ethics

PO4 Investigations PO9 Individual & Team Work

PO5 Modern Tools PO10 Communication Skills

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 INDEX
CONTENT

VISION & MISSION

PO’S

PSO’S

LIST OF FIGURES

S.NO. CHAPTER – 1: Introduction to VLSI Design 12-16

1.
1.1 The basic of VLSI 12
2.
1.2 Key components of VLSI Design 12-13
3.
1.3 VLSI Design Process 13-14
4.
1.4 Types of VLSI Design 15
5. 1.5 Challenges in VLSI design 15-16
6. 1.6 Applications in VLSI design 16

7. CHAPTER – 2: Digital Logic Design 17-34

8. 2.1 Boolean algebra 17
9. 2.2 Don’t care condition 17
10. 2.3 Gate’s implementation 18-36

11. CHAPTER – 3: Synchronous and Asynchronous 35-54

sequential circuits
12. 3.1 Introduction 37-39
13.
3.2 Latches 39-41
14. 3.3 Flip Flops 41-54
15. 3.4 Shift Registers 54-58
16. 3.5 PLA 58-60
17.
CHAPTER – 4: VHDL 56-68
18. 4.1 Introduction 61
19.
4.2 Data types in VHDL 61-62
20.
4.3 Levels of Abstraction 62

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21.
4.4 VHDL Design Units 62-63
22.
4.5 Key concept on Dataflow Model 63-67
23. 4.6 Key concept of Behavioral Model 67-72

24. 4.7 key concept of structural model 72-76

CONCLUSION 76-77

8
 List of Figures

Fig .No. Name of the Figures Pg.No

1.0 Introduction to VLSI Design 13

1.1 Components of VLSI Design 14

1.2 VLSI Design Process 15

1.3 Types of VLSI Design 16

2.0 NAND Gate Truth Table 18

2.1 NOR Gate Truth Table 18

2.2 Implementation of AND Gate and NAND Gate 19

2.2.0 NOR Implementation 19

2.3 Combinational Circuit 19

2.4 Block Diagram of Half Adder 20

2.4.0 Truth Table of Half Adder 20

2.5 Block diagram of Full Adder 20

2.5.0 Truth table of Full Adder 20

2.6 Block diagram of Half Subtractor 21

2.6.0 Truth table of the Half Subtractor 21

2.7 Block diagram of Binary Full Subtractor 21

2.7.0 Truth table of Binary Full Subtractor 22

2.8 Circuit diagram for parallel Adder 22

2.9 Circuit diagram for parallel subtractor 22

9
2.10 Block diagram of Carry look A Header 23

2.11 Block Diagram of Magnitude comparator 24

2.11.0 Truth table of Magnitude comparator 24

2.12 Logic diagram of 1-bit comparator 24

2.13 Block diagram of 2-bit comparator 24

2.13.0 Truth Table of 2-bit comparator 25

2.14 Logic diagram of 2-bit comparator 25

2.15 BCD Adder 26

2.16 Block Diagram of 2*4 Decoder 26

2.16.0 Truth table for 2*4 Decoder 26

2.16.1 Logic diagram of 3*8 Decoder 27

2.17 Block Diagram of 4*2 Encoder 27

2.17.0 Truth Table of 4*2 Encoder 27

2.17.1 Logic Diagram of 4*2 Encoder 28

2.18 Truth Table For Priority Encoder 28

2.18.0 Block Diagram of 4*1 Multiplexer 28

2.19.0 Truth Table of 4*1 Multiplexer 29

2.19.1 Logic Diagram of 4*1 Multiplexer 29

2.20 Block Diagram of 8*1 Multiplexer 29

2.20.0 Truth Table of 8*1 Multiplexer 30

2.21 Block Diagram 1*4 Demultiplexer 32

2.22 Block diagram of boolean logic 32

2.23 Code Converters Truth Table 33

2.23.0 Logic Diagram of Code Converter 34

3.1 Sequential Logic Circuits 35

3.2 SR Flip Flop 35

3.3 Combinational Logic Circuit 36

3.4 Sequential Logic Circuits 36

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 3.5 SR latch 38

3.6 Gated D-Latch 38

3.7 Edge-Triggered Flip Flop 39

3.8 Truth Table For Set-Reset Function 40

3.9 JK-Flip Flop 41

3.9.0 Truth Table of JK-Flip Flop Function 41

3.10 T-FlipFlop 42

3.10.0 Truth Table For T-Flip Flop 43

3.11 Truth Table of T-function 43

3.12 D-Flip Flop 44

3.12.0 Truth Table D-Flip Flop 45

3.13 Block Diagram Of Master-Slave Flip Flop 45

3.13.0 Master Slave JK-Flip Flop 46

3.13.1 Timing Diagram for Master Slave Diagram 46

3.13.2 Truth Table For Master Slave Flip Flop 47

3.14 Block Diagram Of Serial In-Serial Out Register 50

3.15 Block Diagram Of Serial In-Parallel Out Shift Registers 50

3.16 Block Diagram Of Parallel In-Serial Out Shift Registers 51

3.17 Block Diagram Of Parallel In-Parallel Out Shift Registers 51

3.18 Block Diagram Of Bidirectional Shift Registers 52

3.19 Block Diagram of PLA 53

3.19.0 Truth Table of PLA 53

3.20 Block Diagram of PLA Programming 54

3.20.0 Truth Table of PLA Programming 54

11
 Chapter-I
Introduction to VLSI Design

VLSI (Very-Large-Scale Integration) refers to the process of creating integrated circuits (ICs)
by combining thousands or even millions of transistors onto a single chip. This technology has
revolutionized electronics, making possible the creation of powerful, compact, and energy-efficient
devices that form the backbone of modern computing systems, mobile phones, digital cameras, and
more.
VLSI design encompasses a wide range of topics, from the basic principles of semiconductor devices
to the intricate details of chip design, fabrication, and testing. Here's a general overview of VLSI
design:

1.1 The Basics of VLSI

Integrated Circuits (ICs): An IC is a set of electronic circuits on a small flat piece of semiconductor
material, typically silicon. These circuits consist of components like transistors, resistors, capacitors,
and interconnects.
VLSI Technology: VLSI involves placing millions of transistors on a chip. The transistors are
arranged in various configurations to perform complex functions, such as logic gates, memory cells,
and processors. The level of integration distinguishes VLSI from earlier technologies such as SSI
(Small-Scale Integration) and MSI (Medium-Scale Integration).
Scalability: VLSI allows for higher scalability, meaning more complex systems can be integrated
into a single chip, leading to more powerful and compact devices.

Fig.1.1:Introduction to VLSI Design

12
 1.2 Key Components of VLSI Design

Transistor: The fundamental building block in VLSI circuits. The most common types of transistors
used in VLSI are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). These
transistors act as switches and can perform logical operations in digital circuits.
Logic Gates: These are fundamental units in digital circuits, performing basic logical functions
like AND, OR, NOT, NAND, and XOR. A large number of logic gates are combined to form
complex digital circuits in VLSI designs.
Interconnects: The metal wiring that connects different transistors and components on a chip. The
design of interconnects is critical to ensuring that signals travel correctly and efficiently between
different parts of the circuit.
Memory Elements: In VLSI systems, memory blocks (such as SRAM, DRAM, and Flash memory)
are used to store data. Designing memory structures is a key aspect of VLSI.

Fig.1.2:Components of VLSI Design

1.3 VLSI Design Process

The VLSI design process typically involves several key stages:

Specification: This is the first step where the desired functionality of the system is defined. It
involves setting the performance requirements, power consumption limits, and other operational

13
constraints.

Architecture Design: Here, the high-level architecture of the system is developed. This could include
defining the datapath, control logic, and overall structure of the chip.

Logic Design: In this stage, the functional units (such as logic gates) are designed to implement the
required operations. The design is typically described using a hardware description language (HDL) like
Verilog or VHDL.
Circuit Design: This step involves designing the actual electronic circuits that implement the logic
gates and other components. The circuit design focuses on transistor-level details and is usually
optimized for speed, area, and power consumption.
Physical Design: This is the stage where the layout of the chip is created. It involves placing the
components on the chip and routing the interconnects. The goal is to ensure that the design meets the
performance and size requirements while minimizing delays and power loss.
Verification and Testing: Before manufacturing, the design is simulated and verified to ensure it
functions correctly. Various forms of testing, such as functional simulation, timing analysis, and
physical verification, are performed to check for errors or inefficiencies.
Fabrication: Once the design is verified, the chip is sent for manufacturing in a semiconductor foundry.
The fabrication process involves creating the chip by etching patterns onto silicon wafers.
Packaging and Testing: After fabrication, the chip is packaged into a physical form and tested
for performance, reliability, and yield.

Fig.1.3:VLSI Design Process

14
 1.4 Types of VLSI Designs

Digital VLSI Design: This involves designing circuits for digital systems, including microprocessors,
memory systems, and application-specific integrated circuits (ASICs). Digital VLSI circuits use binary
signals (0s and 1s) to perform logical operations.
Analog VLSI Design: Involves the design of circuits that process continuous signals, such as amplifiers,
voltage regulators, and oscillators. Analog VLSI is used in areas like communication systems, sensors,
and power management.
Mixed-Signal VLSI Design: Combines both digital and analog circuits on the same chip. This type of
design is used in systems that require interaction between digital processing and analog signals, such as
data converters (ADC, DAC) and RF circuits.

Fig.1.4:Types of VLSI Design

1.5 Challenges in VLSI Design

Miniaturization: As technology advances, transistors are made smaller, which can lead to increased difficulty in
maintaining proper functionality and performance due to short-channel effects, leakage currents, and power consumption
issues.
Power Consumption: As more components are added to a chip, power management becomes crucial. The design must
minimize power consumption, especially for mobile and portable devices.
Heat Dissipation: High levels of integration lead to increased power density, causing heat buildup. Efficient heat
management techniques are necessary to avoid thermal damage and performance degradation.
Design Complexity: The sheer scale of modern VLSI designs—comprising billions of transistors—requires advanced
tools for automation, verification, and optimization. This makes VLSI design an inherently complex and multidisciplinary
field.

Manufacturing Variability: Variations in the manufacturing process can lead to defects or performance issues in the
final chip. VLSI designers must account for these variations during the design phase.

15
1.6 Applications of VLSI Design

Consumer Electronics: VLSI technology is used in almost every modern electronic device, including
smartphones, laptops, and wearable devices.
Automotive Electronics: VLSI chips are used in automotive systems for safety features (e.g., airbags,
ABS), infotainment, and autonomous driving systems.
Healthcare: VLSI is employed in medical devices like imaging systems, pacemakers, and diagnostic
equipment.
Telecommunications: VLSI is used in network routers, modems, and mobile communication devices.
Computing: VLSI technology underpins processors, GPUs, memory chips, and storage devices used in
everything from personal computers to supercomputers.

16
 Chapter 2:- DIGITAL LOGIC DESIGN

Digital logic design is a system in electrical and computer engineering that uses simple
number values to produce input and output operations.

2.1 BOOLEAN ALGEBRA

● Invented by mathematician George Boole in 1849
● Used by Claude Shannon at Bell Labs in 1938
● To describe digital circuits built from relays

Digital circuit design is based on Boolean Algebra, attributes, postulates, theorems and these allow
minimization and manipulation of logic gates.

2.2 DON’T CARE CONDITION

● You don’t always need all 2n input combinations in an n- variable function

● If you can guarantee that certain input combinations never occur

● If some outputs aren’t used in the rest of the circuit optimizing digital circuits

17
 Fig.2.1: truth table for NAND gate

Fig.2.2:Truth table for NOR gate

Fig.2.3:Truth table for NOR gate

18
Combinational circuit is a circuit in which we combine the different gates in the circuit, for
example encoder, decoder, multiplexer and demultiplexer.
some of the characteristics of combinational circuits are following:

● The output of combinational circuit at any instant of time, depends only on the levels present
at input terminals.

● The combinational circuit do not use any memory. The previous state of input does not
have any effect on the present state of the circuit.
● A combinational circuit can have an n number of inputs and m number of outputs.

19
 Chapter 3:- COMBINATIONAL CIRCUITS

3.1: Block diagram

● Specific functions of combinational circuits Adders, subtractors, multiplexers, comparators,

encoder, Decoder.MSI Circuits and standard cells

3.2 BINARY ADDERS

Half Adder:
● A Half Adder is a combinational circuit with two binary inputs (augends and addend bits and
two binary outputs (sum and carry bits.) It adds the two inputs (A and B) and produces the
sum (S) and the carry (C) bits.

Fig.3.2: Block Diagram

20
 Fig.3.3: Truth Table

Sum=A′B+AB′=A B

Carry=AB
Full Adder:

The full-adder adds the bits A and B and the carry from the previous column called the carry- in Cin
and outputs the sum bit S and the carry bit called the carry out Cout.

Fig.3.4: block diagram

Fig.3.5: Truth table

3.3 Binary Subtractor:

Half Subtractor:

21
A Half subtractor is a combinational circuit with two inputs A and B and two outputs difference(d) and
barrow(b).

Fig.3.6:Truth table d=A′B+AB′=A B ,b=A′B

Fig.3.7: Block diagram

Full subtractor:

The full subtractor perform subtraction of three input bits: the minuend, subtrahend ,
and borrow in and generates two output bits difference and borrow out .

Fig.3.8: Block diagram

Fig.3.9: Truth Table

22
PARALLEL ADDER AND SUBTRACTOR
A binary parallel adder is a digital circuit that adds two binary numbers in parallel form and produces
the arithmetic sum of those numbers in parallel form

ig.3.10: parallel adder

Fig.3.11: parallel subtractor

CARRY LOOK_A HEAD ADDER

● In parallel-adder, the speed with which an addition can be performed is governed by the
time required for the carries to propagate or ripple through all of the stages of the adder.
● The look-ahead carry adder speeds up the process by eliminating this ripple carry delay.

23
 CARRY LOOK-A- HEAD ADDER

Fig.3.12: block diagram

MAGNITUDE COMPARATOR

Magnitude comparator takes two numbers as input in binary form and determines whether one
number is greater than, less than or equal to the other number.

1.Bit Magnitude Comparator:

A comparator used to compare two bits is called a single bit comparator.

Fig.3.13: Block diagram

24
 Fig.3.14: Truth table of Magnitude comparator

Fig.3.15: Logic diagram of 1-bit comparator

2 Bit magnitude comparator :

Fig.3.16: Block diagram

25
 Fig.3.17: Truth table

Fig.3.18: Logic diagram of 2-bit comparator

BCD ADDER
perform the addition of two decimal digits in BCD, together with an input carry from a previous stage.
When the sum is 9 or less, the sum is in proper BCD form and no correction is needed. When the sum
of two digits is greater than 9, a correction of 0110 should be added to that sum, to produce the
proper BCD result. This will produce a carry to be added to the next decimal position.

26
 Fig.3.19: Logic diagram

3.4 DECODER
● A binary decoder is a combinational logic circuit that converts binary information from the n
coded inputs to a maximum of 2n unique outputs.
● We have following types of decoders 2x4,3x8,4x16…

Fig.3.20:Block diagram of 2x4 decoder

Fig:3.21:Truth table

27
 DECODERS

Fig:3.22:Higher order decoder implementation using lower order. Ex:4x16 decoder

using 3x8 decoders.

3.5 ENCODERS
● An Encoder is a combinational circuit that performs the reverse operation of
Decoder. It has maximum of 2n input lines and ‘n’ output lines.
● It will produce a binary code equivalent to the input, which is activeHigh.

28
 Fig.3.23:block diagram of 4x2 encoder

Fig3.24:Truth Table

Fig3.25:Logic Diagram
3.6 Priority encoder:

A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0.
Here, the input, Y3 has the highest priority, whereas the input, Y 0 has the lowest
priority.

29
 Fig 3.26: Truth table for Priority encoder

3.7 MULTIPLEXERS

● Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and
single output line. One of these data inputs will be connected to the output based on the values of
selection lines.
● We have different types of multiplexers 2x1,4x1,8x1,16x1,32x1……

Fig 3.27: Block diagram of 4x1 multiplexer

30
 Fig 3.28: Logic diagram of 4x1 multiplexer

Now, let us implement the higher-order Multiplexer using lower-order Multiplexers.

fig 3.29: Block diagram of 8x1 Multiplexer

f(A1 , A2 , A3 ) =Σ(3,5,6,7) implementation using 4x1 mux

Method:1

Fig 3.30:truth table

31
32
Method:2

Fig.3.31:Block diagram of 4x1 mux

Fig.3.32:Truth table of 4x1 mux

3.8 Demultiplexer
● A demultiplexer is a device that takes a single input line and routes it to one of several digital
output lines.

● demultiplexer of 2n outputs has n select lines, which are used to select which output line to
send the input.

● We have 1x2,1x4,8x1…. Demultiplexers.

33
 Fig.3.33:block diagram and Truth table of 1x4 demux
Boolean functions for each output as

Fig.3.34: block diagram of boolean logic

3.9 CODE CONVERTERS

A code converter is a logic circuit whose inputs are bit patterns representing numbers (or
character) in one code and whose outputs are the corresponding representation in a different
code. Design of a 4-bit binary to gray code converter

Fig.3.35: Truth table

34
K-map simplification :

Fig: 3.36: Logic diagram

35
 CHAPTER:4
SEQUENTIAL CIRCUITS

● Sequential logic circuit consists of a combinational circuit with storage elements

connected as feedback to combinational circuit.
● output depends on the sequence of inputs (past and present)

● stores information (state) from past inputs

Fig.4.1: Sequential logic circuits

● Output depends on Input Previous state of the circuit

● Flip-flop: basic memory element

● State table: output for all combinations of input and previous states(Truth Table)

●
Fig.4.2 SR flip flop

● Sequential circuit receives the binary information from external inputs and with the present
state of the storage

36
 elements together determine the binary value of the outputs.

● The output in a sequential circuit are a function of not only the inputs, but also the present
state of the storage elements.
● The next state of the storage elements is also a function of external inputs and the present state.
● There are two types of sequential circuits:
● Synchronous sequential circuits

It is a system whose behaviour can be defined from the knowledge of its signals at discrete
instants of time.

○ Asynchronous sequential circuits

It depends upon the input signals at any instant of time and the order in which the input changes.
4.1 SEQUENTIAL LOGIC CIRCUITS
● Sequential logic circuit consists of a combinational circuit with storage elements
connected as feedback to combinational circuit
● output depends on the sequence of inputs (past and present)

● stores information (state) from past inputs

Fig.4.3: Sequential logic circuits

● Combinational Circuit gives the same output for a given set of inputs ex: adder always
generates sum and carry, regardless of previous inputs
● Sequential Circuit stores information

● output depends on stored information (state) plus input so a given input might produce
different outputs, depending on the stored information
● example: ticket counter

● advances when you push the button output depends on previous state

37
 useful for building ―memoryǁ elements and ―state machines

4.2 STORAGE ELEMENTS

● Storage elements in a digital circuit can maintain a binary state Indefinitely, until directed by
an input signal to switch states. The major difference among various storage elements are the
number of input they posses and the manner in which the inputs affect the binary state. There
are two types of storage elements
1. Latc hes

2. FlipFlops

● Storage elements that operate with signal level are referred as latch and those controlled by a
clock transition are referred as flipflops.

LATCHES:
● A latch has a feedback path, so information can be retained by the device. Therefore, latches
can be memory devices, and can store one bit of data for as long as the device is powered. As
the name suggests, latches are used to "latch onto" information and hold in place. Latches are
very similar to flip-flops, but are not synchronous devices, and do not operate on clock edges
as flip-flops do. Latch is a level sensitive device.
● Latch is a monostable multivibrator

FLIP FLOPS:
● A flip-flop is a circuit that has two stable states and can be used to store state information. A
flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied

38
 to one or more control inputs and will have one or two outputs. It is the basic storage element
in sequential logic. Flip-flops and latches are fundamental building blocks of digital
electronics systems used in computers, communications, and many other types of systems.
Flipflop is a edge sensitive device.
SR LATCH:
● An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals
and relies only on the state of the S and R inputs. In the image we can see that an SR flip-flop
can be created with two NOR gates that have a cross-feedback loop. SR latches can also be
made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes
called an SR latch.

Fig.4.4: SR latch
● R is used to ―resetǁ or ―clearǁ the element – set it to zero. S is used to ―setǁ the element –set
it to one.

● If both R and S are one, out could be either zero or one.

● quiescentǁ state -- holds its previous value. note: if a is 1, b is 0, and vice versa
GATED D-LATCH:
● The D latch (D for "data") or transparent latch is a simple extension of the gated SR latch that
removes the possibility of invalid input states. Two inputs: D (data) and WE (write enable)

● when WE = 1, latch is set to value of D S = NOT(D), R = D when WE = 0, latch holds

previous value S = R = 1

Fig.4.5 : Gated D-Latch

39
 ● A flip flop is an electronic circuit with two stable states that can be used to store

● binary data. The stored data can be changed by applying varying inputs. Flip-flops and latches
are fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems. Flip-flops and latches are used as data
storage elements. There are 4 types of flipflops.
Flip-Flops:
● RS flip flop

● JK flip flop

● D flip flop

● T flip flop
Applications:
● These are the various types of flip-flops being used in digital electronic circuits and the
applications like Counters, Frequency Dividers, Shift Registers, Storage Registers.

EDGE-TRIGGERED FLIP FLOPS:

Characteristics :

● State transition occurs at the rising edge or falling edge of the clock pulse respond to the
input only during these periods Edge-triggered Flip Flops (positive) respond to the input only

at this time.

Fig.4.6: Edge trigger flip flop

SR Flip-Flop :

40
 ―SETǁ the device (meaning the output = ―1ǁ), and is labelled S and one which will
―RESETǁ the device (meaning the output = ―0ǁ), labelled R.The reset input resets the flip-
flop back to its original state with an output Q that will be either at a logic level ―1ǁ or logic
―0ǁ depending uponthis set/reset condition. A basic NAND gate SR flip-flop circuit provides
feedback from both of its outputs back to its opposing inputs and is commonly used in
memory circuits to store a single data bit. Then the SR flip-flop actually has three inputs, Set,
Reset and its current output Q relating to its current state or history.

Fig.4.7 : Truth Table for this Set-Reset Function

JK flip flop:
● The JK Flip-flop is similar to the SR Flip-flop but there is no change in state when the J and
K inputs are both LOW. The basic S-R NAND flip-flop circuit has many advantages and uses
in sequential logic circuits but it suffers from two basic
● switching problems.

● The Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided

● if Set or Reset change state while the enable (EN) input is high the correct latchinaction may
not occur

● Then to overcome these two fundamental design problems with the SR flip-flop design, the
JK flip Flop was developed by the scientist name Jack Kirby. The JK flip flop is basically a
gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or
invalid output condition that can occur when both inputs S and Rare equal to logic level ―1ǁ.
Due to this additional clocked input, a JK flip-flop has four possible input combinations,
● ―logic 1ǁ, ―logic 0ǁ, ―no changeǁ and ―toggleǁ. The symbol for a JK flip flop is similar to
that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a clock
input.

41
 ● Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S
and K = R.
● The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input
NAND gates with the third input of each gate connected to the outputs at Q and
● Q. This cross coupling of the SR flip-flop allows the previously invalid condition of S = ―1ǁ
and R = ―1ǁ state to be used to produce a ―toggle actionǁ as the two inputs are now
interlocked.
● If the circuit is now ―SETǁ the J input is inhibited by the ―0ǁ status of Q through the lower
NAND gate. If the circuit is ―RESETǁ the K input is inhibited by the ―0ǁ status of Q
through the upper NAND gate. As Q and Q are always different we can use them to control
the input. When both inputs J and K are equal to logic ―1ǁ, the JK flip floptoggles as shown
in the following truth table.

○
Fig.4.8:JK flip flop function
The Truth Table for the JK Function :
● Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its
two input terminals, either SET or RESET to be active at any one time thereby eliminating
the invalid condition seen previously in the SR flip flop circuit. Also when both the J and
● The K inputs are at logic level ―1ǁ at the same time, and the clock input is pulsed ―HIGHǁ,
the circuit will ―toggleǁ

from its SET state to a RESET state, or visa- versa.

● This results in the JK flip flop acting more like a T-type toggle flip-flop when both terminals
are―HIGHǁ.

42
 Fig.4.9: Truth table of JK function
T - FLIP FLOP:

○ We can construct a T flip flop by any of the following methods. Connecting the
output feedback to the input, in SR flip flop.
○ Connecting the XOR of T input and Q PREVIOUS output to the Data input, in D flip
flop. Hard – wiring the J and K inputs together and connecting it to T input, in JK flip
– flop.

43
 Fig.4.10: T-flip flop function

● T flip – flop is an edge triggered device i.e. the low to high or high to low transitions on a
clock signal of narrow triggers that is provided as input will cause the change in output state
of flip – flop. T flip – flop is an edge triggered device.

Truth Table of T flip – flop

Fig 4.11 : Truth table of t-flip flop

44
 ● If the output Q = 0, then the upper NAND is in enable state and lower NAND gate is in
disable condition. This allows the trigger to pass the S inputs to make the flip – flop in SET
state i.e. Q = 1.
● If the output Q = 1, then the upper NAND is in disable state and lower NAND gate is in
enable condition. This allows the trigger to pass the R inputs to make the flip – flop in RESET
state i.e. Q =0. In simple terms, the operation of the T flip – flop is When the T input is low,
then the next state of the T flip flop is the same as the present state.
● T = 0 and present state = 0 then the next state = 0 T = 1 and present state = 1 then the next
state = 1

● When the T input is high and during the positive transition of the clock signal, the next state
of the T flip – flop is the inverse of the present state. T = 1 and present state = 0 then the next
state = 1 T= 1 and present state = 1 then the next state = 0
Applications :
● Frequency Division Circuits.

● 2 – Bit Parallel Load Registers.

● T flip – flop is an edge triggered device i.e. the low to high or high to low transitions on a
clock signal of narrow triggers that is provided as input will cause the change in output state
of flip – flop. T flip – flop is an edge triggered device.
Truth Table of T flip – flop

Fig.4.12: truth table of t-function

● If the output Q = 0, then the upper NAND is in enable state and lower NAND gate is in
disable condition. This allows the trigger to pass the S inputs to make the flip – flop in SET
state i.e. Q = 1.

45
 ● If the output Q = 1, then the upper NAND is in disable state and lower NAND gate is in
enable condition. This allows the trigger to pass the R inputs to make the flip – flop in RESET
state i.e. Q =0. In simple terms, the operation of the T flip – flop is When the T input is low,
then the next sate of the T flip flop is same as the present state.
● state. T = 1 and present state = 0 then the next state = 1 T= 1 and pT = 0 and present state
= 0 then the next state = 0 T = 1 and present state = 1 then the next state = 1
● When the T input is high and during the positive transition of the clock signal, the next state
of the T flip – flop is the inverse of present resent state = 1 then the next state = 0

Applications:
● Frequency Division Circuits.
● 2 – Bit Parallel Load Registers.
D FLIP FLOP:

● The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to
prevent the S and R inputs from being at the same logic level One of the main disadvantages
of the basic SR NAND Gate Bistable circuit is that the indeterminate input condition of SET
= ―0ǁ and RESET = ―0ǁ is forbidden.
● his state will force both outputs to be at logic ―1ǁ, overriding the feedback latching action
and whichever input goes to logic level ―1ǁ first will lose control, while the other input still
at logic―0ǁ controls the resulting state of the latch.
● But in order to prevent this from happening an inverter can be connected between the ―SETǁ
and the ―RESETǁ inputs to produce another type of flip flop circuit known as a Data Latch,
Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more
generally called. The D Flip Flop is by far the most important of the clocked flip-flops as it
ensures that inputs S and Rare never equal to one at the same time. The D-type flip-flops are
constructed from a gated SR flip- flop with an inverter added between the S and the R inputs
to allow for a single D (data) input.
● Then this single data input, labelled ―Dǁ and is used in place of the ―Setǁ signal, and the
inverter is used to generate the complementary ―Resetǁ input thereby making a level-
sensitive D-type flip-flop from a level-sensitive SR-latch as now S = D and R = not D as
shown.

46
 Fig.4.13: D-flip flop block diagram

● We remember that a simple SR flip-flop requires two inputs, one to ―SETǁ the output and
one to ―RESETǁ the output. By connecting an inverter (NOT gate) to the SR flip-flop we can
―SETǁ and ―RESETǁ the flip-flop using just one input as now the two input signals are
complements of each other. This complement avoids the ambiguity inherent in the SR latch
when both inputs are LOW, since that state is no longer possible. Thus this single input is
called the ―DATAǁ input. If this data input is held HIGH the flip flop would be ―SETǁ and
when it is LOW the flip flop would change and become ―RESETǁ. However, this would be
pointless since the output of the flip flop would always change on every pulse applied to this
data input.
● To avoid this an additional input called the ―CLOCKǁ or ―ENABLEǁ input is used to
isolate the data input from the flip flop’s latching circuitry after the desired data has been
stored. The effect is that D input condition is only copied to the output Q when the clock input
is active. This then forms the basis of another sequential device called a D Flip Flop.
● The ―D flip flopǁ will store and output whatever logic level is applied to its data terminal so
long as the clock input is HIGH. Once the clock input goes LOW the ―setǁ and ―resetǁ inputs
of the flip-flop are both held at logic level ―1ǁ so it will not change state and store whatever
data was present on its output before the clock transition occurred. In otherwords the output
is―latched ǁat either logic ―0ǁ or logic ―1ǁ.

47
 fig.4.14:Truth Table for the D-type Flip Flop
MASTER SLAVE FLIPFLOP
● Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as the
master and the other as a slave. The figure of a master-slave J-K flip flop is shown below.

Fig.4.15: Block diagram of Master -slave flip flop

● From the above figure you can see that both the J-K flip flops are presented in a series
connection. The output of the master J-K flip flop is fed to the input of the slave J-K flip flop.
The output of the slave J-K flip flop is given as a feedback to the input of the master J-K flip
flop. The clock pulse [Clk] is given to the master J-K flip flop and it is sent through a NOT
Gate and thus inverted before passing it to the slave J-K flip flop.
● The truth table corresponding to the working of the flip- flop shown in Figure is given by
Table I. Here it is seen that the outputs at the master-part of the flip-flop (data enclosed in red
boxes) appear during the positive-edge of the clock (red arrow). However at this instant the
slave-outputs remain latched or unchanged. The same data is transferred to the output pins of
the master-slave flip-flop (data enclosed in blue boxes) by the slave during the negative edge
of the clock pulse (blue arrow). The same principle is further emphasized in the timing
diagram of master-slave flip-flop shown by Figure 3. Here the green arrows are used to
48
 indicate that the slave-output is nothing but the master- output delayed by half-a-clock cycle.
Moreover it is to be noted that the working of any other type of master-slave .flip-flop is
analogous to that of the master slave JK flip-flop explained here.

○
Fig.4.16: master -slave JK flip flop

Fig.4.17: Timing diagram for master -slave jk flip flop

49
 ○

■ Fig 4.18: Truth table for master -Slave JK flip flop

50
 ○

51
 ○

SHIFT REGISTERS
● Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They
are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
the input of the next flip-flop. Most of the registers possess no characteristic internal sequence
of states. All the flip-flops are driven by a common clock, and all are set or reset
simultaneously. Shift registers are divided into two types.

52
Uni directional shift registers :
1. Serial in – serial out shift register

2. Serial in – parallel out shift register

3. Parallel in – serial out shift register

4. Parallel in – parallel out shift register

Bidirectional shift registers

1. Left shift register

2. Right shift
Serial in – Serial out shift register:

● A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The
operation of the circuit is as follows. The register is first cleared, forcing all four outputs to
zero. The input data is then applied sequentially to the D input of the first flip-flop on the left
(FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data word
to be 1001. The least significant bit of the data has to be shifted through the register from
FF0.

Fig.4.19: Block diagram of shift register serial in – serial out

● In order to get the data out of the register, they must be shifted out serially. This can be
done destructively or non-destructively. For destructive readout, the original data is lost and
at the end of the read cycle, all flip-flops are reset to zero.

53
Serial in – Parallel out shift register:

Fig.4.20: Block diagram of serial in – parallel out shift register

● The difference is the way in which the data bits are taken out of the register. Once the data
are stored, each bit appears on its respective output line, and all bits are available
simultaneously.

● In the animation below, we can see how the four-bit binary number 1001 is shifted to the Q
outputs of the register.
Parallel in – serial out shift register:
● A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-
flops and NAND gates for entering data to the register.

54
 Fig.4.21: Block diagram of parallel in – serial out shift register

● D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the
least significant bit. To write data in, the mode control line is taken to LOW and the data is
clocked in. The data can be shifted when the mode control line is HIGH as SHIFT is active
high. The register performs right shift operation on the application of a clock pulse, as shown
in the animation below.

Parallel in –parallel out shift register:

● For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits. The following circuit is a four-
bit parallel in parallel out shift register constructed by D flip-flops.

55
 Fig.4.22: Block diagram of parallel in – parallel out shift register
● The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is
clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously.
Bidirectional Shift Registers:
● The registers discussed so far involved only right shift operations. Each right shift operation
has the effect of successively dividing the binary number by two. If the operation is reversed
(left shift), this has the effect of multiplying the number by two. With suitable gating
arrangement a serial shift register can perform both operations.
● A bidirectional, or reversible, shift register is one in which the data can be shift either left or
right. A four-bit bidirectional shift register using D flip-flops is shown below

56
 ●

Fig.4.23: Block diagram of Bidirectional shift register

● Here a set of NAND gates are configured as OR gates to select data inputs from the right or
left adjacent bi table, as selected by the LEFT/RIGHT control line.

● The animation below performs right shift four times, then left shift four times. Notice the
order of the four output bits are not the same as the order of the original four input bits.
PROGRAMMABLE LOGIC ARRAY
● A programmable logic array (PLA) is a type of logic device that can be programmed to
implement various kinds of combinational logic circuits.

Fig.4.24: Block diagram of PLA

● The device has a number of AND and OR gates which are linked together to give output or
further combined with more gates or logic circuits.

● PLA architecture is more efficient than a PROM.

57
 ● PLA architecture has two sets of programmable fuses due to which PLA devices are difficult
to manufacture, program and test.

● PLA is used to provide control over data path.

● PLA is used as a counter.

● PLA is used as decoders.

● PLA is used as a BUS interface in programmed

Simplification of PLA :
● Careful investigation must be undertaken in order to reduce the number of distinct product
terms, PLA has a finite number of AND gates.
● Both the true and complement of each function should be simplified to see which one can be
expressed with fewer product terms and which one provides product terms that are common
to other functions.
Example :
Implement the following two Boolean functions with a PLA: F1(A, B, C) =? (0, 1, 2, 4)
F2(A, B, C) =? (0, 5, 6, 7) . The two functions are simplified in the maps of given figure

Fig.4.25: truth table of PLA

PLA table by simplifying the function

○ Both the true and complement of the functions are simplified in sum of products.

58
○ We can find the same terms from the group terms of the functions of F1, F1’,F2 and F2’
which will make the minimum terms.
○ F1 = (AB +AC + BC)’ F2 = AB + AC + A’B’C’

Fig.4.26: Truth table for PLA Programming

○
Fig.4.27:BlockdiagramofPLAProgramming

59
 CHAPTER 5: VHDL

VHDL (VHSIC Hardware Description Language) is a hardware description language used to

model, simulate, and design digital electronic systems. Originally developed for the U.S. Department
of Defense, VHDL allows engineers to describe the behavior and structure of electronic circuits, such
as logic gates, flip-flops, and processors, at various levels of abstraction (from high-level
functional descriptions to low-level gate-level
implementations).

Key aspects of VHDL include:

1. Concurrency: VHDL is designed to model hardware's inherently parallel nature,

allowing for the description of multiple components working simultaneously.
2. Hierarchical Design: VHDL supports a modular design approach, where complex
systems can be broken down into smaller, manageable components.
3. Simulation: VHDL is used to simulate how a digital system will behave before actual
hardware is built.
4. Synthesis: VHDL can be synthesized into actual hardware by targeting specific
FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated
Circuit) technologies.
The language includes constructs for defining entities (modules), architectures (implementations),
signals (connections), and processes (sequential behaviors). VHDL is widely used in industries that
require precise control of hardware behavior, such as telecommunications, aerospace, and consumer
electronics. VHDL, the term "types" can refer to data types used to define variables and signals, and
also to different levels of abstraction for describing hardware systems. Below is a breakdown of both:
Data Types in VHDL
Data types define the kind of values that variables, signals, and constants can hold. Some of the key
data types in VHDL include:

● Scalar Types: Represent single values.

○ Integer: Whole numbers (e.g., 0, -5, 42).

○ Bit: Represents binary values ('0' or '1').

○ Boolean: Represents logical true or false (TRUE or FALSE).

60
 ○ Character: A single character (e.g., 'A', '1').

● Access Types: Similar to pointers in other programming languages, access types point to a
location in memory (used in VHDL for dynamic memory allocation).
● Array Types: Collections of elements of the same type.

○ Array of bits: A vector of bits (e.g., bit_vector(7 down to 0) for 8 bits).

○ Array of integers: An array of integers (e.g., integer_array(1 to 10)).

● File Types: Used to handle file input and output.

● Record Types: Similar to structures in C/C++, used to group different types of data
together (e.g., a person record with name, age, and height).
● Access/Pointer Types: For dynamic allocation of memory, akin to pointers in C/C++.

● Enumerated Types: A set of named values (e.g., type state is (idle, busy, done)).

● Floating-Point Types: For representing real numbers with a fractional part (e.g., real).
Levels of Abstraction in VHDL
VHDL can describe hardware at different levels of abstraction, which can be categorized as follows:

● Behavioral Level: Describes the functionality of the system without specifying how it's
implemented.

○ Example: Describing a 4-bit adder with a simple if statement or mathematical

operation.

● Register-Transfer Level (RTL): Describes data flow between registers and the operations
on that data (often used for synthesis).
○ Example: Describing how data is transferred between flip-flops and the logical
operations between them.
● Structural Level: Describes the system in terms of components and how they are connected
(similar to wiring a circuit).
○ Example: Instantiating gates, flip-flops, and other modules, and specifying their
interconnections.
● Gate Level: Describes the circuit in terms of logic gates (AND, OR, NOT, etc.), often used
for low-level optimizations or detailed simulation.
VHDL Design Units
VHDL uses several types of design units to describe hardware:
● Entity: Defines the interface of a module (e.g., input and output ports).

61
 ● Architecture: Describes the internal implementation of a module, which can include both
behavior and structural elements.
● Configuration: Specifies which architecture to use with a given entity (useful when there are
multiple architectural options).

● Package: Contains reusable declarations, such as data types, constants, and subprograms
(functions and procedures).
● Process: Describes sequential behavior within an architecture, executed when certain
conditions or signals change.
These different types of VHDL help in building a comprehensive and structured design flow,
ranging from high-level functional descriptions to detailed gate-level designs suitable for hardware
synthesis.
In VHDL, dataflow refers to a style of modeling where the behavior of a system is described in
terms of how data flows between components, rather than explicitly specifying how operations are
performed step-by-step (as in behavioral modeling). Dataflow modeling captures the relationships
between inputs, outputs, and internal signals through continuous assignments that describe how data
is transferred or transformed.
Key Concepts in Dataflow Modeling
1. Signal Assignment: The core of dataflow modeling is the use of signal assignments, which
describe how signals change in response to other signals.
○ Concurrent Signal Assignment: In VHDL, signal assignments are executed
concurrently. This is

unlike a sequential programming language where instructions are executed one after
the other. In dataflow modeling, the assignment of values to signals happens based on
the logic and the data flowing through the circuit.
○ Assignments are Continuous: Once an assignment is made, the value of a signal is
automatically updated whenever its input signals change, as long as the assignment
expression reflects that change.
Syntax of Signal Assignment in Dataflow

A typical signal assignment in VHDL follows this syntax:

vhdl
Copy code
<signal_name> <= <expression>;
Where:
62
 ● <signal_name> is the signal that will receive a new value.

● <expression> is the value or formula based on other signals.

The assignment is non-blocking, meaning the right-hand side of the assignment is evaluated
continuously, and the left-hand side signal updates whenever the right-hand side expression changes.
5.1 Dataflow Modeling in VHDL
Here’s an example of a simple 2-input AND gate implemented using dataflow modeling in VHDL:

vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_gate is
Port (A : in
STD_LOGIC; B : in
STD_LOGIC;
Y : out STD_LOGIC );
end and_gate;
architecture dataflow of and_gate
is begin
Y <= A AND B; -- Signal assignment, dataflow
description end dataflow;
● The Y <= A AND B; statement describes a continuous dataflow where the signal Y is
continuously assigned the value of A AND B.

● Whenever A or B changes, Y is automatically updated to reflect the new logical AND of A

and B.
Consider a simple 4-bit adder that sums two 4-bit input vectors and generates a 4-bit sum and a
carry-out signal:
vhdl

Copy code
library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder is
Port ( A : in STD_LOGIC_VECTOR(3
downto 0); B : in STD_LOGIC_VECTOR(3
downto 0);
63
 Sum : out STD_LOGIC_VECTOR(3 downto
0); Cout : out STD_LOGIC );
end adder;
architecture dataflow of adder
is begin
Sum <= A + B;
Cout <= '1' when (A(3) and B(3)) = '1' else '0'; -- Dataflow for
carry-out end dataflow;
Here:
● The sum of A and B is assigned to the Sum signal directly (Sum <= A + B;).
● The carry-out signal Cout is determined based on the most significant bits of A and B (a
simple check for a carry from the most significant bit).
Advantages of Dataflow Modeling
● Conciseness: Dataflow modeling allows designers to describe complex systems in a more
concise and high-level manner, as you don't need to specify detailed sequential operations.
● Clear Representation of Logic: It is especially useful when modeling combinational logic,
as it directly represents how data flows through the system.
● Parallel Execution: Since VHDL assignments are concurrent, dataflow naturally captures the
parallel nature of hardware circuits.

Dataflow vs. Behavioral and Structural Modeling

● Behavioral Modeling: This describes the functionality at a higher level (e.g., using processes
and algorithms) without focusing on how it is physically implemented. For example, you
could describe an adder using a process with if or case statements.

● Structural Modeling: Involves describing the components of a system and how they are
interconnected, essentially wiring gates or modules together.
Dataflow vs. Behavioral
5.2 Behavioral Adder (using a process):
vhdl
architecture behavioral of adder is
begin
process(A,
B) begin
Sum <= A + B;

64
 Cout <= (others => '0');

-- Additional logic can be added

here end process;
end behavioral;
Dataflow Adder:
vhdl
Copy code
architecture dataflow of adder is
begin

Sum <= A + B;
Cout <= '1' when (A(3) and B(3)) = '1' else
'0'; end dataflow;
In VHDL, dataflow modeling focuses on how data flows through the system and how signals
are continuously updated based on logical expressions. It is particularly useful for modeling
combinational logic in a concise and parallel manner. By using concurrent signal assignments,
dataflow modeling captures the high-level relationships between inputs and outputs without
specifying detailed sequential behavior.
Behavioral modeling in VHDL is a way of describing how a system behaves or what it does
without explicitly specifying how it is physically implemented (such as specifying gates, flip-flops,
or wires). Instead, you focus on what the system should do its logic or functionality using high-level
constructs like if-else statements, case statements, loops, and processes.
In behavioral VHDL, the emphasis is on the functionality of the circuit rather than its structure
(which is the focus of structural modeling). This approach is particularly useful when designing
complex systems because it allows you to describe high-level functionality with fewer details about
the underlying hardware.
Key Concepts of Behavioral Modeling in VHDL
1. Processes: A process defines a block of code that executes sequentially when certain
conditions are met. Within a process, you can describe logic using if, case, and loop
statements.
2. Sequential Statements: In a process, statements are executed in the order they appear.
These include conditionals (if, case), loops (for, while), assignments (:=, <=), and more.
3. Signals and Variables:

○ Signals: Used to represent values that persist across multiple simulation cycles and are
used for communication between processes (similar to wires in hardware).
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 ○ Variables: Temporary storage used within a process. They update immediately upon
assignment and have local scope to the process in which they are declared.
4. Clocked vs. Unlocked Processes:

○ Clocked processes are typically used to describe sequential logic (like flip-flops or
registers).

○ Unclocked processes are typically used to describe combinational logic.

Syntax of Behavioral VHDL

The basic structure of a behavioral model in VHDL typically includes:

1. Entity Declaration: Describes the inputs and outputs.

2. Architecture: Describes the behavior, which can include processes, conditionals, and
other high-level constructs.

3. Simple Behavioral Adder.

Consider a simple 2-bit adder implemented using behavioral modeling in VHDL.
Entity Declaration
vhdl
Copy code
library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder is
Port (A : in STD_LOGIC_VECTOR(1 downto 0); B : in STD_LOGIC_VECTOR(1 downto
0);
Sum : out STD_LOGIC_VECTOR(1 downto 0); Cout : out STD_LOGIC );
end adder;
Architecture
(Behavioral) vhdl
Copy code
architecture behavioral of adder is
begin
process (A, B)

begin
-- Add the two 2-bit inputs
Sum <= A + B; -- Add the two vectors

66
 Cout <= '1' when (A(1) and B(1)) = '1' else '0'; -- Carry out
logic end process;
end behavioral;

● The process(A, B) ensures that the logic inside the process is executed whenever either A or
B changes.

● Inside the process, we use a simple arithmetic operation (A + B) for the sum and a conditional
operation for the carry-out (Cout).
● The signal assignment Sum <= A + B; means the sum of A and B is continuously assigned to
Sum.

● The Cout is set to '1' if both the most significant bits of A and B are 1 (indicating a carry),
otherwise '0'.
4-Bit Synchronous Counter (Clocked Process)
A 4-bit synchronous counter is a good example of a clocked process in VHDL. A counter updates its
value on each clock cycle, so the process is sensitive to the clock signal.
Entity Declaration
vhdl
Copy code
library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter is
Port ( clk : in
STD_LOGIC; reset : in
STD_LOGIC;
count : out STD_LOGIC_VECTOR(3 downto
0) ); end counter;
Architecture (Behavioral)

vhdl
Copy code
architecture behavioral of counter is
signal cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- Internal signal for the counter
begin
process(clk, reset) begin

67
 if reset = '1' then
cnt <= "0000"; -- Reset the counter
to 0 elsif rising_edge(clk) then
cnt <= cnt + 1; -- Increment the counter on the rising edge of the
clock end if;
end process;
count <= cnt; -- Output the counter
value end behavioral;
● The counter is described using a clocked process: process (clk, reset). The process triggers on
any change to the clk or reset signals.
● Inside the process, the counter is reset to zero when reset = '1', or the counter is incremented
by 1 on each rising edge of the clock (rising_edge(clk)).

● The internal signal cnt holds the counter value, and the value is assigned to the output signal
count at the end of the architecture.
A 2-to-1 Multiplexer (Using Conditional Statements)
This example demonstrates a multiplexer using if-else conditionals in behavioral VHDL. Entity
Declaration.
vhdl
Copy code
library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2to1 is
Port ( A : in
STD_LOGIC; B : in
STD_LOGIC;
sel : in
STD_LOGIC; Y :
out STD_LOGIC );
end mux2to1;
Architecture
(Behavioral) vhdl
Copy code
architecture behavioral of mux2to1
is begin
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 process(A, B,
sel) begin
if sel = '0' then
Y <= A; -- Select A if sel is
0 else
Y <= B; -- Select B if sel is
1 end if;
Advantages of Behavioral Modeling
● High-Level Abstraction: You focus on what the system does (its functionality) rather
than its low-level structure, making the design process quicker and more manageable.

● Flexibility: It’s easier to modify the functionality of the system without worrying
about specific implementation details.
● Compact Code: Behavioral code is usually more concise and easier to understand compared
to structural VHDL, especially for complex systems.
Disadvantages of Behavioral Modeling
● Less Control Over Hardware: Since you don't explicitly define the hardware structure, the
synthesizer decides how to implement the logic, which may not always be optimal for a
specific hardware target (e.g., FPGA or ASIC).
● No Explicit Timing or Structure: It may not provide as much control over the specific timing
of signals and hardware implementation details, which may be necessary for some
applications (like timing-critical designs).
Behavioral modeling in VHDL focuses on describing what a system does rather than how it does
it. By using constructs like if, case, and process, you can describe complex functionality without
delving into the low-level hardware implementation. It provides a high-level, concise way of
modeling systems and is typically used for combinational or sequential logic where the exact
hardware structure is not the primary concern.
5.3 Structural Modeling
The Structural Modeling is very similar to the schematic entry, in this case implemented as text
instead of graphically. As digital designs become more complex, it becomes less likely that
we can use only one of the three-implementation styles seen before. The result is the use of the
hybrid VHDL model. VHDL Syntax Coding Style: Behavioral, Data Flow, Structural, Hybrid.
The term structural modeling is the terminology that VHDL uses for the modular design:

if you are designing a complex project, you should split in two or more simple design in order to
easy handle the complexity.

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The benefits of modular design in VHDL are similar to the benefits that modular design or object-
oriented design provides for higher-level computer languages.
VHDL Structural Modeling Coding Style
Modular designs allow you to pack low-level functionality into modules.

This approach allows a design reuse without the need to reinvent and re-test the wheel every time.
Structural Modeling: Hierarchical approach
Structural Modeling Coding Style: Hierarchical Approach
Next step is the hierarchical approach where you can extend beyond the structural coding modeling.
In this case in the TOP Level design, are instantiated a
● design1

○ sub-design 1

○ sub-design 2

● design2

○ sub-design 3
○ sub-design 4
Structural architecture declaration
In order to instance a component inside a design, you shall:

● Declare the components in the declarative part of the architecture

● Instance the component in the architecture statement section

The declaration section of the architecture is included between the keyword “is” and “begin”
architecture architecture_name of entity_name is

-- ARCHITECTURE declarative part begin

-- ARCHITECTURE statement part end architecture_name;
The statement section or concurrent section of the architecture is included between the keywords
“begin” and “end”.
The component declaration to be inserted in the declarative section of the architecture can be
summarized as follow:
● Copy the entity declaration relative to the component

● Replace the keyword “entity” with the keyword “component”

● Delete keyword “is” . If you use VHDL 1993 standard or above you can leave the keyword
“is”

● Replace the entity name after the keyword “end” with the keyword “component”.
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Component Instantiation
● Copy component declaration in the architecture concurrent area

● Replace the keyword “component” with the instance name and add the keyword “map”
after the generic and port clause.

In order to map generic and port

● Replace the comma with the two symbols equal greater than

● Replace the semicolon with colon.

An example will clarify better than thousand explanations. Structural architecture declaration
example. In this example we want to realize the structural implementation the entity and_or in figure
below AND OR entity structural implementation. There are 4 input ports a, b, d, e and one output
port g. The instance u1 and u2 of the two AND gate are connected to the u3 using two wire named c
and f. Figure above shows the entity declaration for AND2 and OR2 component.
In this moment, we don’t care about the architecture of AND2 and OR2 entity. It could be
structural with other component instantiation or behavioral. Let’s see the architecture of the and_or
entity in order to understand better the structural instantiation
e an
n d_
t or
i is
t
y

p
o
r
t
(

a : i std_
n logi
c;

b : i std_
n logi

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 c;

d : i std_
n logi
c;

e : i std_
n logi
c;

g : o std_logic);
u
t

end and_or;

architecture and_or_a of and_or

is
component and2 -- and2 component
declaration
port(
a : in std_logic;
b : in std_logic;
c : out std_logic);
end component;
component or2 -- or2 component
declaration
port(
a : in std_logic;
b : in std_logic;
c : out std_logic);
end component;
signal c : std_logic; -- wire used to
connect

signal f : std_logic; -- the

component
begin
-- and2 component
instance
u1: and2
port map(
a => a,
b => b,
c => c);
-- and2 component
instance
u2: and2
port map(
a => d,
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b => e,
rt map(

a => c,

b => f,

c => g); end and_or_a;

In the architecture declarative section we found:

● component declaration AND2 and OR2

● signal declaration c and f

In the statement section, we found the component instantiation. Now pay attention to the port
mapping.

● The port a, b and c mapped in the instance u1 are respectively the entity input port a and b,
the internal wire signal c.
● The port a, b and c mapped in the instance u2 are respectively the entity input port d and e,
the internal wire signal f.

The instance u3 has the port a mapped on signal c, input port b on signal f and output port c on entity
output port g. As general rule,

the input/output port of an entity are signal inside the architecture. The input port can be only read,
the output port can be only written.
If you try to read from an output port or try to write to an input port the simulator rises an error and
stops.

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 CONCLUSION
VLSI design is critical for the electronics industry

VLSI technology is a key component in the production of microprocessors, memory chips, and
other ICs. It allows for the creation of smaller, faster, and more powerful devices at a lower cost.
VLSI design is shaping the future of wireless communication

VLSI design is enabling the development of more power-efficient, cost-effective, and highly
integrated wireless devices.
VLSI design requires coding

VLSI designers use a variety of programming languages and tools to create and verify their
designs.
VLSI design involves back-end design steps

Back-end design steps include wafer processing, lithography, etching, ion implantation,
metallization, assembly, and packaging.

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