IRFP460

N-CHANNEL 500V - 0.22Ω - 18.4A TO-247

PowerMesh™II MOSFET

TYPE VDSS RDS(on) ID

IRFP460 500V < 0.27Ω 18.4A

■ TYPICAL RDS(on) = 0.22Ω
■

■
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
( s )
■ NEW HIGH VOLTAGE BENCHMARK
c t
■ GATE CHARGE MINIMIZED

d u 2
3

DESCRIPTION
r o s )
1

™
The PowerMESH II is the evolution of the first
™.
generation of MESH OVERLAY The layout re-
e P c t ( TO-247

l e t
finements introduced greatly improve the Ron*area
figure of merit while keeping the device at the lead-
d u
charge and ruggedness.
s o
ing edge for what concerns swithing speed, gate
r o INTERNAL SCHEMATIC DIAGRAM

O b e P
- l e t
APPLICATIONS
■

( s
SWITH MODE LOW POWER SUPPLIES ) o
(SMPS)
c t
■ HIGH CURRENT, HIGH SPEED SWITCHING
b s
d u
■ DC-AC CONVERTERS FOR WELDING

- O
o
EQUIPMENT AND UNINTERRUPTIBLE
r s )
e P c t (
POWER SUPPLIES AND MOTOR DRIVES

l e t d u
o r o
ABSOLUTE MAXIMUM RATINGS
s
O b Symbol

e P Parameter Value Unit

l
VDS

e
VDGRt Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
500
500
V
V

s o VGS Gate- source Voltage ±30 V

O b ID
ID
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
18.4
11.6
A
A
IDM (●) Drain Current (pulsed) 73.6 A
PTOT Total Dissipation at TC = 25°C 220 W
Derating Factor 1.75 W/°C
dv/dt(1) Peak Diode Recovery voltage slope 3.5 V/ns
Tstg Storage Temperature –65 to 150 °C
Tj Max. Operating Junction Temperature 150 °C
(•)Pulse width limited by safe operating area
(1)ISD ≤18.4A, di/dt ≤100A/µs, V DD ≤ V(BR)DSS, Tj ≤ TJMAX.

May 2001 1/8

 IRFP460

THERMAL DATA
Rthj-case Thermal Resistance Junction-case Max 0.57 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W
Rthc-sink Thermal Resistance Case-sink Typ 0.1 °C/W
Tl Maximum Lead Temperature For Soldering Purpose 300 °C

AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
Avalanche Current, Repetitive or Not-Repetitive
IAR 20 A
(pulse width limited by Tj max)
Single Pulse Avalanche Energy
EAS 960 mJ
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

( s )
OFF
c t
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)

Symbol Parameter
d u
Test Conditions Min. Typ. Max. Unit

V(BR)DSS
Drain-source
r o s
ID = 250 µA, VGS = 0) 500 V
Breakdown Voltage
Zero Gate Voltage
e P c t
VDS = Max Rating( 1 µA
IDSS
Drain Current (VGS = 0)

l e t u
VDS = Max Rating, TC = 125 °C
d
50 µA

IGSS
Gate-body Leakage
Current (VDS = 0)
s o r o
VGS = ±30V ±100 nA

O b e P
ON (1)
- l e t
Symbol

( s )
Parameter
o Test Conditions Min. Typ. Max. Unit
VGS(th)

c t
Gate Threshold Voltage
b s VDS = VGS, ID = 250µA 2 3 4 V
Ω
RDS(on)
u O
Static Drain-source On

d
Resistance
-
VGS = 10V, ID = 9 A 0.22 0.27

ID(on) r o s ) VDS > ID(on) x RDS(on)max,

e P c t (
On State Drain Current
VGS = 10V
18.4 A

l
DYNAMIC
e t d u
s o Symbol
r o Parameter Test Conditions Min. Typ. Max. Unit

O b gfs (1)
e P Forward Transconductance
VDS > ID(on) x RDS(on)max,
ID = 9A
18 S

l e t
Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2980 pF

s o Coss Output Capacitance 410 pF

O b Crss
Reverse Transfer
Capacitance
58 pF

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 IRFP460

ELECTRICAL CHARACTERISTICS (CONTINUED)

SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Delay Time VDD = 250V, ID = 10A 29 ns
RG = 4.7Ω VGS = 10V
tr Rise Time (see test circuit, Figure 3) 21 ns

VDD = 400V, ID = 20A,

Qg Total Gate Charge 95 128 nC
VGS = 10V
Qgs Gate-Source Charge 14.7 nC
Qgd Gate-Drain Charge 41.7 nC

SWITCHING OFF
( s )
Symbol Parameter
c t
Test Conditions Min. Typ. Max. Unit

tr(Voff) Off-voltage Rise Time

d u
VDD = 400V, ID = 20A,
RG = 4.7Ω, VGS = 10V 20 ns

r o )
(see test circuit, Figure 5)

s
tf Fall Time

e P c t ( 21 ns
tc Cross-over Time

l e t d u
58 ns

SOURCE DRAIN DIODE

s o r o
Symbol
ISD
Parameter

O
Source-drain Current b e P Test Conditions Min. Typ. Max.
18.4
Unit
A
ISDM (2)
- l
Source-drain Current (pulsed)
e t 73.6 A
VSD (1)
s )
Forward On Voltage
( o ISD = 18.4A, VGS = 0 1.6 V

c t b s ISD = 20A, di/dt = 100A/µs,

trr

d u - O
Reverse Recovery Time VDD = 100V, Tj = 150°C
(see test circuit, Figure 5)
480 ns

Qrr
r o )
Reverse Recovery Charge

s
5 µC
IRRM

e P t (
Reverse Recovery Current

c
21 A

l e t
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

u
2. Pulse width limited by safe operating area.

d
s o r o
Safe Operating Area Thermal Impedence

O b e P
l e t
s o
O b

3/8
 IRFP460

Output Characteristics Transfer Characteristics

( s )
c t
d u
r o s )
Transconductance
P t (
Static Drain-source On Resistance

e c
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
Gate Charge vs Gate-source Voltage Capacitance Variations

O b e P
l e t
s o
O b

4/8
 IRFP460

Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature

( s )
c t
d u
r o s )
Source-drain Diode Forward Characteristics

e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

5/8
 IRFP460

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

( s )
c t
d u
Fig. 3: Switching Times Test Circuit For
r o s )
Fig. 4: Gate Charge test Circuit
Resistive Load
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times

O b e P
l e t
s o
O b

6/8
 IRFP460

TO-247 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.85 5.15 0.19 0.20
D 2.20 2.60 0.08 0.10
E 0.40 0.80 0.015 0.03
F 1 1.40 0.04 0.05
F1 3 0.11
F2 2 0.07

( s )
F3
F4
2
3
2.40
3.40
0.07
0.11
c t 0.09
0.13
G 10.90
d
0.43 u
H 15.45 15.75 0.60
r o 0.62

s )
L
L1
19.85
3.70
20.15
4.30
0.78
0.14
e P c t (
0.79
0.17
L2 18.50
l e t d
0.72
u
L3 14.20 14.80

s o 0.56
r o 0.58
L4
L5
34.60
5.50
O b e P 1.36
0.21
M 2
- 3
l e t
0.07 0.11
V 5º

( s ) o 5º
V2

c t
60º
b s 60º
Dia 3.55

d u - O
3.65 0.14 0.143

r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

7/8
 IRFP460

( s )
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

s o of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are

b
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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