Name : SHARVAN PHANSIKAR
Roll No : 231060056
Branch : B.Tech Electronics Engineering
Experiment No. 2
Aim :-
To plot CMOS inverter VTC
Software Used :-
LTSpice
Theory :-
A CMOS inverter is the most fundamental logic gate in digital electronics and VLSI design. CMOS stands
for Complementary Metal-Oxide-Semiconductor, which uses a combination of p-channel MOSFET
(PMOS) and n-channel MOSFET (NMOS) transistors. The term complementary refers to the fact that one
transistor is ON while the other is OFF, depending on the input voltage. This complementary action results
in low static power consumption and makes CMOS technology the dominant choice in modern integrated
circuits (ICs). Moreover, CMOS inverters provide a full voltage swing from 00 to VDDV_{DD}, ensuring
reliable logic levels with high noise immunity, and they serve as the fundamental building blocks for
implementing more complex digital circuits such as NAND, NOR, and flip-flops in VLSI systems.
Working :-
The CMOS inverter operates by using the complementary switching action of a PMOS and an NMOS
transistor. When the input voltage is LOW (0 V), the PMOS transistor is turned ON because its gate-to-
source voltage is negative, while the NMOS remains OFF since its gate voltage is below the threshold. As
a result, the output is connected to VDDV through the PMOS, producing a logic HIGH. Conversely, when
the input is HIGH (VDDV), the PMOS turns OFF, and the NMOS turns ON, creating a path from the output
to ground, hence the output becomes logic LOW. For intermediate input values, both transistors conduct
partially, and the output switches rapidly from HIGH to LOW. This sharp transition provides a clear
distinction between logic levels. Thus, the CMOS inverter ensures rail-to-rail output, low static power
consumption, and reliable operation as a fundamental digital circuit element.
Voltage Transfer Characteristics :-
Voltage Transfer Characteristics, the dynamic behavior of a CMOS inverter describes its switching
performance when the input changes with time. Since no logic gate switches instantaneously, the inverter’s
output transition depends on capacitances, resistances, and current drive strength of the MOSFETs.
The static VTC of a CMOS inverter shows the DC relationship between input voltage (Vin) and output
voltage (Vout). However, in real digital circuits, the input is not static — it changes with time. The dynamic
VTC explains the time-dependent behavior of the inverter output when the input transitions from
LOW → HIGH or HIGH → LOW.
The propagation delay (tp) is the time difference between a change in input and the corresponding 50%
change in output. It is the average of:
● tPHL (High → Low delay): Time for output to fall from HIGH (VDD) to LOW (0). This occurs
when input goes HIGH, NMOS conducts and discharges CL.
● tPLH (Low → High delay): Time for output to rise from LOW (0) to HIGH (VDD). This occurs
when input goes LOW, PMOS conducts and charges CL.
Propagation delay increases with higher load capacitance and smaller transistor sizes.
● Rise time (tr): Time taken by Vout to rise from 10% to 90% of VDD.
● Fall time (tf): Time taken by Vout to fall from 90% to 10% of VDD.
Ideally, tr = tf, but practically, PMOS is weaker than NMOS (lower mobility), so rise time is usually
longer than fall time unless transistor sizes are adjusted.
Outputs :-
Calculations :-
Conclusion :-
The CMOS inverter experiment demonstrates the fundamental operation of complementary MOS transistors,
where one device conducts while the other is off, ensuring rail-to-rail output and minimal static power
consumption. The static voltage transfer characteristics (VTC) confirmed the sharp switching behavior,
high noise margins, and full voltage swing from 0V to VDDV, making CMOS highly reliable for digital
logic. The dynamic analysis highlighted the impact of load capacitance on propagation delay, rise time, and
fall time, which are critical parameters in determining inverter speed and power consumption.
