UNIT II - COMBINATIONAL LOGIC CIRCUITS

Propagation Delays, stick diagram, Layout diagrams, Examples of combinational logic design, Elmore’s
constant, Static Logic Gates, Dynamic Logic Gates, Pass Transistor Logic, Power Dissipation, Low Power
Design principles.

2.1 : Delay estimation

 Draw a CMOS inverter. Analyze the switching characteristics during rise time when
Vin change from high to low. (April 2019-7M)
 Derive an expression for the rise time, fall time and propagation delay of a CMOS
inverter. (DEC 2013, APRIL-2015) [Nov 2019] [Nov/Dec 2022]

 Important definitions for delay estimation:

Propagation delay time (tpd):
 Propagation delay time is defined as maximum time from the input crossing 50% to the output
crossing 50%.
Contamination delay time (tcd):
 Contamination delay time is defined as minimum time from the input crossing 50% to the
output crossing 50%.
Rise time (tr):
 Rise time is defined as time for a waveform to rise from 20% to 80% of its steady-state value
Fall time (tf):
 Fall time is defined as time for a waveform to fall from 80% to 20% of its steady-state value
 Edge rate is average of rise and fall time, ( trf) = (tr + tf )/2
Delay estimation response curve:
 When an input changes, the output will retain its old value for at least the contamination delay
and take on its new value in, at most the propagation delay.
 Delays for the output rising is tpdr /tcdr and the output falling is tpdf /tcdf .
 Rise/fall times are also called as slopes or edge rates.
 Propagation and contamination delay times are also called as max-time and min-time
respectively.

Figure: Delay estimation of CMOS inverter

  The gate that charges or discharges a node is called the driver. The gates and wires being
driven, are called the load. Propagation delay is usually called as delay.
 Arrival times and propagation delays are defined separately for rising and falling transitions.
 The delay of a gate may be different from different inputs. Earliest arrival times can also
be computed based on contamination delays.
 Expression of delay for rising output is tPLH = 0.69 RP.CL
Where, RP – effective resistance of pMOS transistor
CL - load capacitance of CMOS inverter.
 Expression of delay for falling o u t p u t
 t pHL=0.69 R N C L
 Where, RN – effective resistance of nMOS transistor
 Propagation delay of CMOS inverter is tP = (tPLH + tPHL) / 2

2.1.1 : RC Delay Model:

Discuss in detail about the resistive and capacitive delay estimation of a CMOS inverter circuit.
(MAY 2013) (or)
Briefly explain about the RC delay model.

 RC delay model approximates the nonlinear transistor I-V and C-V characteristics with an
average resistance and capacitance over the switching range of the gate.

Effective Resistance:

 The RC delay model treats a transistor as a switch in series with a resistor.

 The effective resistance is the ratio of Vds to Ids.
 A unit nMOS transistor is defined to have effective resistance R.
 An nMOS transistor of k times unit width has resistance R/k, because it delivers k times as
much current.
 A unit pMOS transistor has greater resistance, generally in the range of 2R–3R, because of
its lower mobility.
 According to the long-channel model, current decreases linearly with channel length (L) and
hence resistance is proportional to L.

Gate and Diffusion Capacitance:

 Each transistor has gate and diffusion capacitance.

 C is the gate capacitance of a unit transistor. A transistor of k times unit width has
capacitance kC.
 Diffusion capacitance depends on the size of the source/drain region.
 Wider transistors have proportionally greater diffusion capacitance. Increasing channel
length, increases gate capacitance proportionally but does not affect diffusion capacitance.

Equivalent RC Circuits:
  Figure shows equivalent RC circuit models for nMOS and pMOS transistors of
width k with contacted diffusion on both source and drain.
 The pMOS transistor has approximately twice the resistance of the nMOS transistor,
because holes have lower mobility than electrons.

Figure: RC model of nMOS &pMOS transistors

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2.2 : Stick diagram

 Explain about stick diagram in VLSI design. (April 2008)
 Draw the static diagram of CMOS inverter. (April 2019-7M)

 A stick diagram is a cartoon of a chip layout. A "stick diagram" is a paper and pencil tool that
use to plan the layout of a cell.
 The stick diagram resembles the actual layout, but uses "sticks" or lines to represent the
devices and conductors. Figure 17, shows a stick diagram for an inverter.
 The stick diagram represents the rectangles with lines, which represent wires and component
symbols.
 The stick diagram does not represent all the details of a layout, but it makes some relationship
much clearer and it is simple to draw.
 Layouts are constructed from rectangles, but stick diagrams are built from cartoon symbols for
components and wires.

Stick diagram Rules:

 Rule 1: When two or more ‘sticks’ of the same type cross or touch each other, that
represents electrical contact.
 Rule 2: When two or more ‘sticks’ of the different type cross or touch each other, there is
no electrical contact. If electrical contact is needed, we have to show the connection
explicitly.
 Rule 3: When a poly crosses diffusion, it represents a transistor. If a contact is shown, then
it is not a transistor. A transistor exists where a polysilicon (red) stick crosses either an n-
diffusion (green) stick or a p-diffusion (yellow) stick.
 Rule 4: In CMOS, a demarcation line is drawn to avoid touching of p-diff with n-diff. All
pMOS must lie on one side of the line and all nMOS will have to be on the other side.
 Figure 17: Stick diagram for an inverter
The symbols for wires used on various layers are shown in Figure 18.

Figure 18: Symbols for wires used on various layers

 Drawing stick diagrams in color: Red for poly, green for n-diffusion, yellow for p-diffusion,
and shades of blue for metal are typical colors.
 A few simple rules for constructing wires from straight-line segments ensure that, the stick
diagram corresponds to a feasible layout.
 Wires cannot be drawn at arbitrary angles. Only horizontal and vertical wire segments are
allowed.
 Two wire segments on the same layer, which cross are electrically connected.
 Vias to connect wires, which do not normally interact, are drawn as black dots.
 Figure 19, shows the stick figures for transistors.
 Each type of transistor is represented as poly and diffusion crossings, much as in the layout.

Figure 19: Stick figures for transistors

 Area and aspect ratio are also difficult to estimate from stick diagrams.
 Stick diagrams are especially important tools for layouts built from large cells and for testing
the connections between cells.

Example:1
Here is the transistor schematic for a two-input NAND gate:

And here is a stick diagram for the two-input NAND:

Example: 2
Draw the Stick diagram of CMOS Inverter

Example: 3
Draw the Stick diagram of CMOS NOR gate

Example: 4
Draw the stick diagram of [(A . B) +C]’
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2.3 : Layout Design Rules and Gate Layouts

 Draw and explain briefly the n-well CMOS design rules. (NOV 2007, April 2008, MAY 2014)
 Discuss in detail with a neat layout, the design rules for a CMOS inverter.
 Write the layout design rules and draw diagram for four input NAND and NOR. (Nov 2016)
(April 2018)
 State the minimum width and minimum spacing lambda based design rules to draw the
layout. (April 2019-6M)

 Layout rules also referred to as design rules.

 It can be considered as prescription for preparing the photomasks, which are used in the
fabrication of integrated circuits.
 The rules are defined in terms of feature sizes (widths), separations and overlaps.
 The main objective of the layout rules is to build reliable functional circuits in as small
area as possible.
 Layout design rules describe how small features can be and how closely they can be reliably
packed in a particular manufacturing process.
 Design rules are a set of geometrical specifications that dictate the design of the layout masks.
 A design rule set provides numerical values for minimum dimensions and line spacing.
 Scalable design rules are based on a single parameter (λ), which characterizes the resolution of
the process. λ is generally half of the minimum drawn transistor channel length.
 This length is the distance between the source and drain of a transistor and is set by the
minimum width of a polysilicon wire.

Lambda based rule (Scalable design rule):

 Lambda-based rules are round up dimensions of scaling to an integer multiple of λ.
 Lambda rules make scaling layout small. The same layout can be moved to a new process,
simply by specifying a new value of λ.
 The minimum feature size of a technology is characterized as 2λ.
Micron Design Rules (Absolute dimensions):
 The MOSIS rules are expressed in terms of lambda.
 These rules allow some degree of scaling between processes.
 Only need to reduce the value of lambda and the designs will be valid in the next process
down in size.
 These processes rarely shrink uniformly.
 Thus, industry usually uses the actual micron design rules for layouts.
 There are set of micron design rules for a hypothetical 65 nm process.
 We can observe that, these rules differ slightly but not immensely from lambda based rules
with lambda = 0.035 micro meter.
 Upper level metal rules are highly variable depending on the metal thickness. Thicker wires
require greater widths, spacing and bigger vias.

 Two metal layers in an n-well process has the following:

 Metal and diffusion have minimum width and spacing of 4 λ.
 Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below.
 Polysilicon uses a width of 2 λ.
  Polysilicon overlaps diffusion by 2 λ where a transistor is desired and has a spacing
of 1 λ away where no transistor is desired.
 Polysilicon and contacts have spacing of 3 λ from other polysilicon or contacts.
 N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.

Figure: Simplified λ -based design rules with CMOS inverter layout diagram

Design
Rule: Well
Rules:
  The n-well is usually a deeper implant than the transistor source/drain implants.
 Therefore, it is necessary to provide sufficient clearance between the n-well edges and the
adjacent n+ diffusions.
Transistor Rules:
 CMOS transistors are generally defined by at least four physical masks.
 There are active (also called diffusion, diff, thinox, OD, or RX), n-select (also called n-
implant, n-imp, or nplus), p-select (also called p-implant, pimp, or pplus) and polysilicon (also
called poly, polyg, PO, or PC).
 The active mask defines all areas, where n- or p-type diffusion is to be placed or where the
gates of transistor are to be placed.

Contact Rules:
 There are several generally available contacts:
 Metal to p-active (p-diffusion)
 Metal to n-active (n-diffusion)
 Metal to polysilicon
 Metal to well or substrate
Metal Rules:
 Metal spacing may vary with the width of the metal line.
 Metal wire width of minimum spacing may be increased. This is due to etch characteristics
versus large metal wires.
Via Rules:
 Processes may allow vias to be placed over polysilicon and diffusion regions.
 Some processes allow vias to be placed within these areas, but do not allow the vias to the
boundary of polysilicon or diffusion.
Example 1: Inverter
Figure shows a layout for an inverter. The input A can be connected from the top, bottom, or left in
polysilicon. The output Y is available at the right side of the cell in metal. The p-substrate and n-well
must be tied to ground and power, respectively. Well and substrate taps are placed under the power and
ground rails, respectively. Well tap cells are used to limit resistance between power or ground
connections to wells of the substrate. Taps are traditionally used so that VDD and GND are connected to
substrate and n-wells respectively This is used to tie them to VDD and GND levels so that they don’t drift
too much.
Example: NAND3
Draw the gate layout diagram of NAND. (May 2017)
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom

2.4 Introduction (Combinational Logic Circuit):

CMOS logic

 Digital logics are divided into combinational and sequential circuits.

 Combinational circuits are circuits where outputs depend only on the present inputs.
 For sequential or regenerative circuit, the output is not only a function of the current input
data, but also of previous values of the input signals.
 A sequential circuit includes a combinational logic portion and a memory module that holds
the state. Example are registers, counters and memory.
 The building blocks for combinational circuits are logic gates, while the building blocks for
sequential circuits are registers and latches.
 The delay of a logic gate depends on its output current I, load capacitance C and output
voltage swing ΔV.


 Alternative (ratioed circuits, dynamic circuits and pass transistor circuits) CMOS logic
configurations are called circuit families.
 nMOS transistors provide more current than pMOS for the same size and capacitance, so
nMOS networks are preferred.
Examples of combinational circuits
(i) CMOS inverter:

Figure: Inverter (a) schematic (b) symbol Y = A

(ii) Two input NAND gate:

Figure: 2 input NAND gate (a) schematic (b) symbol

Three input NAND gate:

Figure: 3 –input NAND gate Schematic Y=A.B.C

(iii) Two input NOR gate:

Figure: 2-input NOR gate (a) schematic (b) Symbol Y = A + B

Example:
Sketch a static CMOS gate computing Y=(A+B+C).D

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2.5 : Elmore’s Delay

What is meant by Elmore’s delay and give expression for Elmore’s delay?

 The Elmore delay model estimates the delay from a source, switching to one of the leaf
nodes. Delay is the sum over each node i of the capacitance Ci on the node multiplied by
the effective resistance R.
Propagation delay time :

tpd
 R
nodes
itosource
Ci
i

 R1C1  R1  R2 C2 ...  R1  R2 ...  RN CN

 Delay of an ideal fanout-of-1 inverter with no parasitic capacitance is τ = 3RC.
 The normalized delay d relative to this inverter delay:

Figure: RC delay equivalent for series of transistors

Linear delay model

 The RC delay model is one, where delay is a linear function of the fanout of a gate.
 The normalized delay of a gate as d = f + p.
 Where p is the parasitic delay inherent to the gate when no load is attached.
f is the effort delay or stage effort that depends on the complexity.
 Effort delay of the gate is f = gh.
Where g is the logical effort (An inverter has a logical effort of 1).

 Logical effort is defined as the ratio of the input capacitance of a gate to the input capacitance of
 an inverter delivering the same output current.
 h is the fanout or electrical effort. Electrical effort is defined as ratio of the output capacitance to
input capacitance.
 More complex gates have greater logical efforts, indicating that they take longer time to drive a
given fanout.
 For example, the logical effort of the 3-input NAND gate is 5/3.
 The electrical effort can be computed as h  Cout
Cin
Where Cout is the capacitance of the external load being driven and Cin is the capacitance
of the gate.
 Normalized delay vs electrical effort for an idealized inverter and 3-input NAND gate shown
in diagram.
 The y-intercepts indicate the parasitic delay. The slope of the lines is the logical effort.
 The inverter has a slope of 1. The NAND gate has a slope of 5/3.

Design a four input NAND gate and obtain its delay during the transition from high to low.
(April 2018)
Figure shows a model of an n-input NAND gate in which the upper inputs were all 1 and
the bottom input rises. The gate must discharge the diffusion capacitances of all of the internal nodes
as well as the output.

Elmore delay is

Logical effort
Obtain the logical effort and path efforts of the given circuit. (April 2018)
Delay in Multistage Logic Networks:
The figure shows the logical and electrical efforts of each stage in a multistage path as a
function of the sizes of each stage.
The path of interest (the only path in this case) is marked with the dashed blue line. Observe that logical
effort is independent of size, while electrical effort depends on sizes.
The path logical effort G can be expressed as the products of the logical efforts of each stage
along the path.

G  gi

The path electrical effort H can be given as the ratio of the output capacitance the path
must drive divided by the input capacitance presented by the path
C
H  C out ( path)
in( path)

The path effort F is the product of the stage efforts of each stage.
F   fi  gihi

Introduce an effort to account for branching between stages of a path. This branching effort b
is the ratio of the total capacitance seen by a stage to the capacitance on the path.

Conpath  Coffpath
b Conpath

The path branching effort B is the product of the branching efforts between stages.

B  bi

The path effort (F) is defined as the product of the logical, electrical, and branching
efforts of the path. The product of the electrical efforts of the stages is actually BH, not just H.
F = GBH
Compute the delay of a multistage network. The path delay D is the sum of the delays
of each stage. It can also be written as the sum of the path effort delay DF

D   d i  DF  P
DF   f i
P   pi

The product of the stage efforts is F, independent of gate sizes. The path effort delay is
the sum of the stage efforts. The sum of a set of numbers whose product is constant is minimized by
choosing all the numbers to be equal.
The path delay is minimized when each stage bears the same effort. If a path has N stages and
each bears the same effort, that effort must be
fˆ = gi hi = F 1 / N
Thus, the minimum possible delay of an N-stage path with path effort F and path
parasitic delay P is
D = NF 1/ N + P
 It shows that the minimum delay of the path can be estimated knowing only the
number of stages, path effort, and parasitic delays without the need to assign transistor sizes.
The capacitance transformation formula is used to find the best input capacitance for a
C *g
Ci i  outi  i
gate given the output capacitance it
n f
drives.
At the end of the path, apply the capacitance transformation to determine the size of each
stage. Check the arithmetic by verifying that the size of the initial stage matches the specification.
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2.6 Pass Transistor

Write short notes on pass transistor.

nMos

pMOS

 Transistors can be used as switches

Signal Strength
 How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0, But degraded or weak 1
 pMOS pass strong 1,But degraded or weak 0
 Thus NMOS are best for pull-down network
 Thus PMOS are best for pull-up network

**********************************************************************

2.7 Transmission Gates

Write short notes on transmission gates (TG).
 By connecting an nMOS and a pMOS transistor in parallel, we obtain a switch that turns on
when a 1 is applied to the gate terminal in which 0’s and 1’s are both passed in an
acceptable fashion.

 We term this a transmission gate or pass gate.

 In a circuit where only a 0 or a 1 hwaswtwo b.Ee np gasgs eTdr,et eh e.caopmpro pri at e

transistor (n or p) can be deleted, reverting to a single nMOS or pMOS device.

 Note that, both the control input and its complement are required by the transmission
gate. This is called double rail logic.

 When the control input is low( control =0), the switch is open, and when the control is
high (control=1) the switch is closed.
  Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1

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2.8 Cascaded CMOS Inverter

Derive the generalized expression for propagation delay of N-cascaded CMOS inverters if ‘N’ is
even and if ‘N’ is odd. [Nov 2019]

 Assume a signal is available at the output of a minimum size inverter and that it is
to drive a load CL.

The average propagation delay associated with driving this load directly is,

Where, tapd is the average logic stage delay and CG is the input capacitance of the reference

inverter. For any integer n ≥ 1, define α by the expression,

Alternatively, n can be represented in terms of α as

This structure is composed of a cascade of n inverters each sized by the 4 : 1 sizing rule and each with
a drive capability that is α times as large as the previous stage.

The width and length of the kth stage can be characterized by the equations,

18
where,

Wdk and Ldk are device dimensions correspond to the pull down transistor

Wuk and Luk are device dimensions correspond to the pull up transistor

The load on the kth stage CLK is,

The average propagation delay of the first inverter is αtapd

Hence, it follows from above equation with mi = 0 and (fi / θi) = α

The total delay for the cascade is,

Let r be the ratio between the propagation delays of the direct drive circuit and of the geometric
cascade approach.

It is our goal to determine n and α to minimize r and thus minimize the propagation delay in driving
the load.

19
Therefore, n can be eliminated from the expression for r to obtain the expression.

20
 *******************************************************************

2.9 Circuit Families

Briefly discuss about the classification of circuit families and comparison of the circuit families.
(May 2014, APRIL-2015)
Draw the CMOS logic circuit for the Boolean expression Z= A(B C)  DE and explain. (April
2018)

Draw and explain the function of static CMOS.

2.10.1: Static CMOS
 Static CMOS circuits with complementary nMOS pulldown and pMOS pullup networks are
used for the majority of logic gates in integrated circuits.

Figure: Static CMOS inverter

Advantages of static CMOS:
 Static CMOS circuits have good noise margins
 Static CMOS circuits are fast, low power, easy to design.
 Static CMOS circuits are widely supported by CAD tools.
 Static CMOS circuits are available in standard cell libraries.
Drawback of static CMOS
 It requires both nMOS and pMOS transistors for each input.
 It has a relatively large logical effort.
 Gate delay is increased.

a. Bubble pushing
 CMOS stages are inherently inverting, so AND and OR functions must be built from NAND
and NOR gates.
 DeMorgan’s law helps with this conversion:
A.B  A 
BAB
A.B

21
 Figure: Bubble pushing with DeMorgan’s law
 A NAND gate is equivalent to an OR of inverted inputs.
 A NOR gate is equivalent to an AND of inverted inputs.
 The same relationship applies to gates with more inputs.
 Switching between these representations is easy and is often called bubble pushing.

b. Compound Gates
 Static CMOS also efficiently handles compound gates computing various inverting
combinations of AND/OR functions in a single stage.
 The function F = AB +CD can be computed with an AND-OR INVERT- 22 (AOI22) gate and
an inverter, as shown in Figure.

 Logical effort of compound gates can be different for different inputs.

 Figure shows, how logical efforts can be estimated for the AOI21, AOI22 and a more
complex compound AOI gate.
Q: Design a circuit described by the Boolean function Y=[A.(B+C)(D+E)]’using CMOS
logic. (NOV 2021)

Figure: Logical efforts and parasitic delays of AOI gates

22
c. Input ordering delay effect

 The logical effort and parasitic delay of different gate inputs are different.
 Consider the falling output transition occurring, when one input hold a stable 1 value and the
other rises from 0 to 1.
 If input B rises last, node x will initially be at VDD – Vt = VDD, because it was pulled up
through the nMOS transistor on input A.
 The Elmore delay is (R/2)(2C) + R(6C) =7RC=2.33 τ
 If input A raises last, node x will initially be at 0 V, because it was discharged through the
nMOS transistor on input B.
 No charge must be delivered to node x, so the Elmore delay is simply R(6C) =6RC =2τ.

Figure: 2 –input NAND gate Schematic Y=A.B

 We define the outer input to be the input closer to the supply rail (e.g., B) and the inner input
to be the input closer to the output (e.g., A).
 Therefore, if one signal is known to arrive later than the others, the gate is faster when that
signal is connected to the inner input.

d. Asymmetric gates

 When one input is far less critical than another, even symmetric gates can be made
asymmetric to favor the late input at the expense of the early one.
 In a series network, this involves connecting the early input to the outer transistor and making
the transistor wider, so that, it offers less series resistance when the critical input arrives.
 In a parallel network, the early input is connected to a narrower transistor to reduce the
parasitic capacitance.
 Consider the path in Figure (a). Under ordinary conditions, the path acts as a buffer between A
and Y.
 When reset is asserted, the path forces the output low.
 If reset only occurs under exceptional circumstances and take place slowly, the circuit should
be optimized for input-to-output delay at the expense of reset.
 This can be done with the asymmetric NAND gate in Figure (b).

23
 Figure: Resettable buffer optimized for data input

e. Skewed gates
What is meant by skewed gate and give functions of skewed gate with schematic diagrams?

 One input transition is more important than the other. HI-skew gates to favor the rising output
transition. LO-skew gates to favor the falling output transition.
 This favoring can be done by decreasing the size of the noncritical transistor.
 The logical efforts for the rising (up) and falling (down) transitions are called gu and gd,
respectively.
 Figure (a) shows, how a HI-skew inverter is constructed by downsizing the nMOS transistor.
 This maintains the same effective transition, while reducing the input capacitance relative to the
unskewed inverter of Figure (b).
 Thus reducing the logical effort on that critical transition to gu = 2.5/3 =5/6.
 The logical effort for the falling transition is estimated by comparing the inverter to a smaller
unskewed inverter with equal pulldown current, shown in Figure (c), giving a logical effort of
gd =2.5/1.5 =5/3.

Figure: Logical effort calculation for HI-skew inverter

 Figure shows, HI skew and LO-skew gates with a skew factor of two. Skewed gates
are sometimes denoted with an H or an L on their symbol in a schematic.

24
 Figure: List of skewed gates

f. P/N ratios
 By accepting a slower rise delay, the pMOS transistors can be downsized to reduce input
capacitance and average delay significantly.
 P/N ratio is defined as the ratio of PMOS transistor width to NMOStransistor width. For
processes, a mobility ratio of µn/µp = 2.

g. Multiple threshold voltages

 Some CMOS processes offer two or more threshold voltages.
 Transistors with lower threshold voltages produce more ON current, but also leak
exponentially more OFF current.
 Libraries can provide both high- and low-threshold versions of gates.
 The low-threshold gates can be used carefully to reduce the delay of critical paths.
 Skewed gates can use low-threshold devices on, only the critical network of transistors.

 Realize the following function Y=(A+BC)D+E using static CMOS logic. (April 2019-6M)

25
Example: Realize the following function Y= [AB+C (D+E)]’ using static CMOS logic. [May 2021
(model)]

Example: Implement the following expression in static CMOS logic fashion using no more than
10 transistors. Y = (AB + ACE + DE + DCB)’ [Nov 2019]

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2.10.2 : Ratioed Circuits:

Write short notes on ratioed circuits. (Nov 2016)

 The ratioed gate consists of an nMOS pulldown network and pullup device called the static
load.
 When the pulldown network is OFF, the static load pulls the output to 1.
 When the pulldown network turns ON, it fights the static load.
 The static load must be weak enough that, the output pulls down to an acceptable 0. Hence,
there is a ratio constraint between the static load and pulldown network.

Advantage: Stronger static loads produce faster rising outputs.

Disadvantages:
o Degrade the noise margin and burn more static power when the output is 0.
26
 o A resistor is a simple static load, but large resistors consume a large layout area in
typical MOS processes.
 Another technique is to use an nMOS transistor with the gate tied to VGG (Shown in fig.(b)). If
VGG =VDD, the nMOS transistor will only pull up to VDD – Vt.
 Figure (c) shows depletion load ratioed circuit.

Figure: nMOS ratioed gates

2.10.3 : pseudo nMOS

Explain the detail about pseudo-nMOS gates with neat circuit diagram. (April/May 2011)
(Nov/Dec 2013)

 Figure (a) shows a pseudo-nMOS inverter.

 The static load is built from a single pMOS transistor that has its gate grounded, so it is always
ON.
 The beta ratio affects the shape of the transfer characteristics and the VOL of the inverter.
 Larger relative pMOS transistor size offer faster rise time, but less sharp transfer
characteristics.
 Drawback: Pseudo-nMOS gates will not operate correctly if VOL >VIL of the receiving gate.

Figure (a): pseudo nMOS inverter Figure: D.C Charateristics

 Figure shows several pseudo-nMOS logic gates.

27
 Implement NAND gate using pseudo- nMOS logic. (Nov 2013, May 2021[model])

Figure: Pseudo-nMOS logic gates

2.10.4 : Ganged capacitor:

 Figure shows pairs of CMOS inverters ganged together.

 The truth table is given in Table, showing that the pair compute the NOR function. Such a
circuit is sometimes called a symmetric 2 NOR, or ganged CMOS.

Figure: symmetric 2 NOR gate.

Table: Operation of symmetric NOR

 When one input is 0 and the other 1, the gate can be viewed as a pseudo-nMOS circuit
with appropriate ratio constraints.
 When both inputs are 0, both pMOS transistors turn on in parallel, pulling the output
high faster than they would, in an ordinary pseudo nMOS gate.
 When both inputs are 1, both pMOS transistors turn OFF, saving static power dissipation.

2.10.5 : Differential Cascode voltage switch with pass gate logic (DCVSPG)

Explain about DCVSL logic with suitable example. (May 2017)

 Cascode Voltage Switch Logic (CVSL) seeks the benefits of ratioed circuits without the static
power consumption.
 It uses both true and complementary input signals and computes both true and complementary
outputs using a pair of nMOS pulldown networks, as shown in Figure (a).

28
  The pulldown network f implements the logic function as in a static CMOS gate, while f uses
inverted inputs feeding transistors arranged in the conduction complement.
 For any given input pattern, one of the pulldown networks will be ON and the other OFF.
 The pulldown network that is ON will pull that output low.
 This low output turns ON the pMOS transistor to pull the opposite output high.
 When the opposite output rises, the other pMOS transistor turns OFF, so no static power
dissipation occurs.
 Figure (b) shows a CVSL AND/NAND gate.
Advantage:
 CVSL has a potential speed advantage because all of the logic is performed with nMOS
transistors, thus reducing the input capacitance.

Figure: CVSL gates

**********************************************************************************
2.11:Dynamic CMOS design:

Describe the basic principle of operation of dynamic CMOS, domino and NP domino logic
with neat diagrams. (NOV 2011) [April / May 2023]

Dynamic Circuits:

 Ratioed circuits reduce the input capacitance by replacing the pMOS transistors connected to
the inputs with a single resistive pullup.
 The drawbacks of ratioed circuits include
o Slow rising transitions,
o Contention on the falling transitions,
o Static power dissipation and a nonzero VOL.
 Dynamic circuits avoid these drawbacks by using a clocked pullup transistor rather than a
pMOS that is always ON.
 Figure compares (a) static CMOS, (b) pseudo-nMOS, and (c) dynamic inverters.

29
 Figure: Comparison of (a) static CMOS, (b) pseudo-nMOS, and (c) dynamic inverters
 Dynamic circuit operation is divided into two modes, as shown in Figure.
(i) During precharge, the clock ф is 0, so the clocked pMOS is ON and initializes the output Y
high.
(ii) During evaluation, the clock is 1 and the clocked pMOS turns OFF. The output may
remain high or may be discharged low through the pulldown network.

Figure: Precharge and evaluation of dynamic gates

Advantages:
 Dynamic circuits are the fastest used circuit family because they have lower input
capacitance and no contention during switching.
 Zero static power dissipation.
Disadvantags:
 They require careful clocking, consume significant dynamic power and are sensitive to noise
during evaluation mode.
Foot transistor:
 In Figure (c), if the input A is 1 during precharge, contention will take place because both the
pMOS and nMOS transistors will be ON.
 When the input cannot be guaranteed to be 0 during precharge, an extra clocked evaluation
transistor can be added to the bottom of the nMOS stack.
 To avoid contention as shown in the below figure, extra transistor is sometimes called as foot
is added.

Figure: Footed dynamic inverter

 The given below figure shows generic footed and unfooted gates.

30
 Figure: Generalized footed and unfooted dynamic gates

 The given below figure estimates the falling logical effort of both footed and
unfooted dynamic gates.

Figure: List of dynamic gates

 The pull down transistor’s width is chosen to give unit resistance. Precharge occurs while the
gate is idle and takes place more slowly.
 Therefore, the precharge transistor width is chosen for twice unit resistance.
 This reduces the capacitive load on the clock and the parasitic capacitance at the expense of
greater rising delays.
 Footed gates have higher logical effort than their unfooted concept but are still an
improvement over static logic.
 The parasitic delay does increase with the number of inputs, because there is more diffusion
capacitance on the output node.
 A fundamental difficulty with dynamic circuits is the monotonicity requirement. While a
dynamic gate is in evaluation, the inputs must be monotonically rising.
 That is, the input can start LOW and remain LOW, start LOW and rise HIGH, start HIGH and
remain HIGH, but not start HIGH and fall LOW.
 Figure shows waveforms for a footed dynamic inverter in which the input violates
monotonicity.

31
 Figure: Monotonicity problem
 During precharge, the output is pulled HIGH.
 When the clock rises, the input is HIGH, so the output is discharged LOW through the
pulldown network.
 The input later falls LOW, turning off the pulldown network. However, the precharge
transistor is also OFF, so the output floats, staying LOW rather than rising.
 The output will remain low until the next precharge step.
 The inputs must be monotonically rising for the dynamic gate to compute the correct function.
 Unfortunately, the output of a dynamic gate begins HIGH and monotonically falls LOW
during evaluation.
 This monotonically falling output X is not a suitable input to a second dynamic gate expecting
monotonically rising signals, as shown in the below figure.
 Dynamic gates sharing the same clock cannot be directly connected.
 This problem is often overcome with domino logic

 Figure: Incorrect connection of dynamic gates

The charge sharing problem occurs when the charge which is stored at the output node in the
pre-charge phase is shared among the junction capacitance of transistors in the evaluation phase.
Charge sharing may degrade the output voltage level or even cause an erroneous output value.

To overcome the dynamic charge sharing and soft- node leakage problems in NORA CMOS
structures, a circuit technique called Zipper CMOS can be used. The basic circuit architecture of
Zipper CMOS is essentially identical to NORA CMOS, with the exception of the clock signals.

2.13 Domino logic

32
 Explain the domino logic families with neat 38
diagrams. (NOV 2012,by:
Prepared APRIL-2015, Nov 2017)
Mr.B.Arun kumar, AP/ECE,SAN

 The dynamic-static pair together is called a domino gate.

 The monotonicity problem can be solved by placing a static CMOS inverter between
dynamic gates, as shown in figure (a).
 This converts the monotonically falling output into a monotonically rising signal suitable
for the next gate, as shown in figure (b).
 A single clock can be used to precharge and evaluate all the logic gates within the chain.
 The dynamic output is monotonically falling during evaluation, so the static inverter output
is monotonically rising.
 Therefore, the static inverter is usually a HI-skew gate to favor this rising output. Observe
that precharge occurs in parallel, but evaluation occurs sequentially.

Figure: Domino gates

2.14 : Dual Rail Domino Logic:

 Dual-rail domino gates encode each signal with a pair of wires. The input and output signal
pairs are denoted with _h and _l, respectively.
 Table summarizes the encoding. The _h wire is asserted to indicate that the output of the gate
is “high” or 1. The _l wire is asserted to indicate that the output of the gate is “low” or 0.
 When the gate is precharged, neither _h nor _l is asserted. The pair of lines should never be
both asserted simultaneously during correct operation.

Table: Dual-rail
33 domino signal encoding
39
  Dual-rail domino gates accept both true and complementary inputs and compute both true and
complementary outputs, as shown in Figure (a).
 This is identical to static CVSL circuits except that the cross-coupled pMOS transistors are
instead connected to the precharge clock.
 Therefore, dual-rail domino can be viewed as a dynamic form of CVSL, sometimes called
DCVS.
 Figure (b) shows a dual-rail AND/NAND gate and Figure (c) shows a dual-rail XOR/XNOR
gate. The gates are shown with clocked evaluation transistors, but can also be unfooted.

Figure: Dual-rail domino gates

Disadvantages:
 It requires more area, wiring and power.
 Dual-rail structures lose the efficiency of wide dynamic NOR gates.
Application:
 It is useful for asynchronous circuits.
2.15 : Keepers

Explain the
 keeper
Dynamic logic family
circuits with
also neat
suffer diagrams.
from charge leakage on the dynamic node.
Briefly discuss
 If athe signal node
dynamic integrity issues in dynamic
is precharged design.
high and then left (April 2018,
floating, NOV 2018)
the voltage on the
dynamic node will drift over time due to subthreshold, gate and junction leakage.
 Dynamic circuits have poor input noise margins.
 If the input rises above Vt,, while the gate is in evaluation, the input transistors will
turn ON weakly and can incorrectly discharge the output.
 Both leakage and noise margin problems can be addressed by adding a keeper circuit.
 Figure shows a conventional keeper on a domino buffer. The keeper is a weak
transistor that holds, or staticizes, the output at the correct level when it would
otherwise float.
 When the dynamic node X is high, the output Y is low and the keeper is ON to prevent
X from floating.
 When X falls, the keeper initially opposes the transition, so it must be much weaker
than the pulldown network.
40
34
  Eventually Y rises, turning the keeper OFF and avoiding static power dissipation.

Figure: Conventional keeper

 The keeper must be strong enough to compensate for any leakage current drawn when the
output is floating and the pulldown stack is OFF.
 Strong keepers also improve the noise margin, because when the inputs are slightly above Vt,
the keeper can supply enough current to hold the output high.

2.15.1 : Differential keeper:

 Figure shows a differential keeper for a dual-rail domino buffer.
 When the gate is precharged, both keeper transistors are OFF and the dynamic outputs float.
As one of the rails evaluates low, the opposite keeper turns ON.
 The differential keeper is fast, because it does not oppose the falling rail.
 As long as one of the rails is guaranteed to fall promptly, the keeper on the other rail will turn
on before excessive leakage or noise causes failure.

Figure: Differential keeper

2.15.2 : Secondary precharge devices
 Dynamic gates are subject to problems with charge sharing.
 For example, consider the 2-input dynamic NAND gate in Figure (a). Suppose the output Y is
precharged to VDD and inputs A and B are low.

Figure: Secondary precharge transistor

 Also suppose that the intermediate node x had a low value from a previous cycle.
 During evaluation, input A rises, but input B remains low, so the output Y should remain high.
 However, charge is shared between CX and CY, shown in Figure (b). This behaves as a
capacitive voltage divider and the voltages equalize at
41
35
2.15.3 : Charge sharing:

 Charge sharing is serious when the output is lightly loaded (small CY ) and the internal
capacitance is large.
 If the charge-sharing noise is small, the keeper will eventually restore the dynamic output to
VDD.
 If the charge-sharing noise is large, the output may flip and turn off the keeper, leading to
incorrect results.
 Charge sharing can be overcome by precharging some or all of the internal nodes with
secondary precharge transistors.
 These transistors should be small, because they only charge the small internal capacitances
and their diffusion capacitance slows the evaluation.
 It is sufficient to precharge every other node in a tall stack.

Figure: Charge-sharing noise

2.15.4 : NP and Zipper Domino

Describe the basic principle of operation of NP domino logic. (NOV 2011)

 The HI-skew inverting static gates are replaced with predischarged dynamic gates using
pMOS logic.
 A footed dynamic p-logic NAND gate is shown in Figure (b). When ф is 0, the first and third
stages precharge high while the second stage predischarges low.
 When ф rises, all the stages evaluate. Domino connections are possible, as shown in Figure
(c).
 The design style is called NP Domino or NORA Domino (NO RAce).

 NORA has two major drawbacks.

(i) The logical effort of footed p-logic gates is worse than that of HI-skew gates.

42
36
 (ii) NORA is extremely susceptible to noise.

 In an ordinary dynamic gate, the input has a low noise margin (about Vt ), but is strongly
driven by a static CMOS gate.
 The floating dynamic output is more prone to noise from coupling and charge sharing, but
drives another static CMOS gate with a larger noise margin.
 In NORA, however, the sensitive dynamic inputs are driven by noise prone dynamic outputs.
 Besides drawback and the extra clock phase requirement, there is little reason to use NORA.
 Zipper domino is a closely related technique, that leaves the precharge transistors slightly ON
during evaluation by using precharge clocks. This swing between 0 and V DD – |Vtp| for the
pMOS precharge and Vtn and VDD for the nMOS precharge.

Figure : NP Domino

**********************************************************************************

37
2.12: Pass Transistor Logic:

Explain Pass transistor logic with neat sketches. (April 2008)

Explain the pass transistor logic and show how complementary pass transistor logic and
double pass transistor logic are applied for 2: 1 multiplexer. [May 2021][Apr/May 2022]

 In pass-transistor circuits, inputs are applied to the source/drain diffusion terminals.

 These circuits build switches using either nMOS pass transistors or parallel pairs of nMOS
and pMOS transistors called as transmission gates.
 The nMOS transistors pass ‘0’s well but 1’s poorly. Figure (a) shows an nMOS transistor with
the gate and drain tied to VDD.
 Initially at Vs = 0. Vgs > Vtn, so the transistor is ON and current flows.
 Therefore, nMOS transistors attempting to pass a 1 never pull the source above VDD – Vtn. This
loss is called a threshold drop.
 The pMOS transistors pass 1’s well but 0’s poorly.
 If the pMOS source drops below |Vtp|, the transistor cuts off.
 Hence, pMOS transistors only pull down to a threshold above GND, as shown in Figure (b).

Figure : Pass Transistor threshold drops

 Figures show an implementation of the AND function and 2x1 multiplexer using only NMOS
transistors.

AND Logic 2x1 multiplexer

 In AND gate, if the B input is high, the top transistor is turned ON and copies the input A to
the output F.
 When B is low, the bottom pass transistor is turned ON and passes a 0.
 In 2x1 multiplexer, if the S selection input is high, the top transistor is turned ON and allows
input A to the output Y.
 When S is low, the bottom pass transistor is turned ON and passes the B input.
 An NMOS device is effective at passing a 0 but is poor at pulling a node to VDD. When the
pass transistor pulls a node high, the output only charges up to VDD -Vtn.

38
Application:
 Pass transistors are essential to the design of efficient 6-transistor static RAM cells used
in modern systems.

Formal Method for P-T Logic Derivation

Complementary function can be implemented from the same circuit structure by applying
complementary principle:
Complementary Principle: Using the same circuit topology, with pass signals inverted,
complementary logic function is constructed in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle: Using the same circuit topology, with gate signals inverted, dual logic function is
constructed.
Following pairs of basic functions are dual:
 AND-OR (and vice-versa)
 NAND-NOR (and vice-versa)
 XOR and XNOR are self-dual (dual to itself)

39
Complementary: AND NAND
Duality: AND OR

2.12.1 : Differential Pass Transistor Logic / Complementary Pass Transistor Logic (CPL)
 For high performance design, a differential pass-transistor logic family, called CPL, is
commonly used.
 The basic idea is to accept true and complementary inputs and produce true and
complementary outputs.
 A number of CPL gates (AND/NAND, OR/NOR, and XOR/NXOR) are shown in Figure.
 Since the circuits are differential, complementary data inputs and outputs are always available.
 Both polarities of every signal eliminate the need for extra inverters, as is often the case in
static CMOS or pseudo-NMOS.
 CPL belongs to the class of static gates, because the output-defining nodes are always
connected to either VDD or GND through a low resistance path.
 This is advantage for the noise flexibility.

Figure: Complementary pass-transistor logic (CPL).

Formal Method for CPL Logic Derivation (AND, NAND, OR, NOR)
(a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed)

(b) Express the value of the function in each cube in terms of input signals

40
(c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one

common node, which is the output of NMOS pass-transistor network

Example: Realize XOR and XNOR gate using CPL. [Nov 2019]

Example: Realize 3 – input AND and NAND gate using CPL.

2.12.2 Double Pass Transistor Logic (DPL)

 Double Pass Transistor Logic is a double rail form of CMOS transmission gate optimized
to use single pass transistors where only a known 0 or 1 needs to be passed.
 It passes good high and low logic levels without the need for level restoring devices.
 DPL uses both nMOS and pMOS switches to realize the desired functions.

41
  This provides a full swing on the output.
 No extra transistors are required for swing restoration.
 A DPL gate consists of both true and complementary inputs / outputs and hence is a dual
rail logic circuit.

Example: Realize XOR gate using Double Pass Transistor Logic (DPL).

Synthesis Rules
 Two NMOS branches cannot be overlapped covering logic 1s. Similarly, two PMOS branches
cannot be overlapped covering logic 0s.
 Pass signals are expressed in terms of input signals or supply. Every input vector has to be
covered with exactly two branches.
 At any time, excluding transitions, exactly two transistor branches are active (any of the pairs
NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i.e. they both provide output
current.

Complementary Principle: Complementary logic function in DPL is generated after the

following modifications:

 Exchange PMOS and NMOS devices. Invert all pass and gate signals
Duality Principle: Dual logic function in DPL is generated when:

42
 EC3552-VLSI AND CHIP DESIGN
UNIT-II

 PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged.
Example: Realize AND and NAND gate using DPL.

Example: Realize full adder (sum circuit) using Double Pass Transistor Logic (DPL).

2.16 : CMOS with transmission gates

 Discuss in detail the characteristics of CMOS Transmission gates.(May 2016, May 2017, Nov 2017)
 Explain Transmission gates with neat sketches. (April 2008, April 2018)
 List out limitations of pass transistor logic. Explain any two techniques used to overcome
limitations. (NOV 2018)
 A transmission gate in conjunction with simple static CMOS logic is called CMOS with
transmission gate.
 A transmission gate is parallel pairs of nMOS and pMOS transistor.
 A single nMOS or pMOS pass transistor suffers from a threshold drop.
 Transmission gates solve the threshold drop but require two transistors in parallel.
 The resistance of a unit-sized transmission gate can be estimated as R for the purpose of delay
estimation.
 EC3552-VLSI AND CHIP DESIGN
UNIT-II

 Current flow the parallel combination of the nMOS and pMOS transistors. One of the
transistors is passing the value well and the other is passing it poorly.
 A logic-1 is passed well through the pMOS but poorly through the nMOS.
 Estimate the effective resistance of a unit transistor passing a value in its poor direction as
twice the usual value: 2R for nMOS and 4R for pMOS.

Figure: CMOS Transmission gate

 The given below figure shows the parallel combination of resistances. When passing a 0, the
resistance is R || 4R = (4/5)R.
 The effective resistance passing a 1 is 2R || 2R = R.
 Hence, a transmission gate made from unit transistors is approximately R in either direction.
 Transmission gates are built using equal-sized nMOS and pMOS transistors.
 Boosting the size of the pMOS transistor only slightly improves the effective resistance while
significantly increasing the capacitance.

Figure: Effective resistance of a unit transmission gate

 Figure (a) redraws the multiplexer to include the Inverters that drive the diffusion inputs but
to exclude the output inverter. Figure (b) shows this multiplexer drawn at the transistor level.

Figure: CMOSTG in a 2-input inverting multiplexer

*****************************************************************************
 EC3552-VLSI AND CHIP DESIGN
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2.17 :

2.18 : Power dissipation:

 Explain the static and dynamic power dissipation in CMOS circuits with necessary
diagrams and expressions. (DEC 2011, Nov 2015, NOV 2016, May 2017, May 2010)
 What are the sources of power dissipation in CMOS and discuss various design techniques
to reduce power dissipation in CMOS? (Nov 2012, May 2013, Nov 2014, May 2016)
 Derive an expression for dynamic power dissipation. (April 2019, Nov 2019, May
2021)[April / May 2023]

 The instantaneous power P (t) consumed by a circuit element is the product of the current and
the voltage of the element
P (t ) = I (t )V (t )

 The energy consumed over time interval T is the integral of the instantaneous power
T

E   P(t) dt
0

 The average power

is P  1
T

E 
T 0
P(t)
avg dt
T
 EC3552-VLSI AND CHIP DESIGN
UNIT-II

Power is expressed in units of Watts (W). Energy is usually expressed in Joules ( J)

 By Ohm’s Law, V = IR, so the instantaneous power dissipated in the resistor is
V2 (t) 2
PR (t)  R  I R (t) R
R
 This power is converted from electricity to heat. VDD supplies power proportional to its
current PVDD (t) =IDD (t) VDD
 When the capacitor is charged from 0 to VC, it stores energy EC

 Figure shows a CMOS inverter driving a load capacitance.

 When the input switches from 1 to 0, the pMOS transistor turns ON and charges the load to
VDD.
 According to EC equation the energy stored in the capacitor is

 The energy delivered from the power supply is

 Gate switches at some average frequency fsw.

 Over some interval T, the load will be charged and discharged Tfsw times.
 Then, the average power dissipation is

 This is called the dynamic power because it arises from the switching of the load.
 Because most gates do not switch every clock cycle, it is often more convenient to express
switching frequency fsw as an activity factor α times the clock frequency f.
 The dynamic power dissipation may be rewritten as

 The activity factor is the probability that the circuit node transitions from 0 to 1, because that
is the only time the circuit consumes power.
 A clock has an activity factor of α = 1 because it rises and falls every cycle.
 The total power of a circuit is calculated as,
Pdynamic = Pswitching + Pshort circuit
 EC3552-VLSI AND CHIP DESIGN
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2.17.1 : Dynamic power:

 Dynamic power consists mostly of the switching power.

 The supply voltage VDD and frequency f are known by the designer.
 To estimate dynamic power, one can consider each node of the circuit.
 The capacitance of the node is the sum of the gate, diffusion, and wire capacitances on the
node.
 The activity factor can be estimated using switching probability or measured from logic
simulations.
 The effective capacitance of the node is, its true capacitance multiplied by the activity factor.
 The switching power depends on the sum of the effective capacitances of all the nodes.

2.17.1.1 :Sources of dynamic power dissipation:

 Dynamic dissipation due to
 Charging and discharging load capacitances as gates switchs.
 “Short-circuit” current while both pMOS and nMOS stacks are partially ON

2.17.1.2 : Low Power Design Principles / Reducing dynamic power dissipation:

 Explain various ways to minimize the static and dynamic power dissipation. (Nov 2013, May 2015)
 Discuss the low power design principles in detail. (Nov 2017)
 Low power design involves considering and reducing each of the terms in switching power.
i. As VDD is a quadratic term, it is good to select the minimum VDD.
ii. Choose the lowest frequency.
iii. The activity factor is reduced by putting unused blocks to sleep.
iv. Finally, the circuit may be optimized to reduce the overall load capacitance.
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 EC3552-VLSI AND CHIP DESIGN
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 Switching power is consumed by delivering energy to charge a load capacitance,

then dumping this energy to GND.

Activity factor:
 If a circuit can be turned OFF entirely, the activity factor and dynamic power go to zero.
 Blocks are typically turned OFF, by stopping the clock called as clock gating.
 The activity factor of a logic gate can be estimated by calculating the switching probability.
(a) Clock gating:
 Clock gating, AND’s a clock signal with an enable to turn OFF the clock to idle
blocks.
 The clock enable must be stable, while the clock is active.
 Figure shows how an enable latch can be used to ensure the enable does not change
before the clock falls.

Capacitance:
 Switching capacitance comes from the wires and transistors in a circuit.
 Wire capacitance is minimized through good floor planning and placement.
 Device-switching capacitances is reduced by choosing smaller transistors.
Voltage:
 Voltage has a quadratic effect on dynamic power.
 Therefore, choosing a lower power supply significantly reduces
power consumption.
 The chip may be divided into multiple voltage domains, where each domain is
optimized for the needs of certain circuits.
a. Voltage domains:
 Selecting, which circuits belong in which domain and routing power supplies to
multiple domains.
 Figure (Voltage domain crossing) shows direct connection of inverters in two
domains using high and low supplies, VDDH and VDDL, respectively.

b. Dynamic voltage scaling (DVS):

Q: Describe how dynamic voltage scaling can reduce dynamic power dissipation. (NOV 2021)
 Systems can save large amounts of energy by reducing the clock frequency, then
reducing the supply voltage.
 This is called dynamic voltage scaling (DVS) or dynamic voltage/frequency scaling
(DVFS).
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 EC3552-VLSI AND CHIP DESIGN
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 It determines the supply voltage and clock frequency sufficient to complete the
workload on schedule or to maximize performance without overheating.

 Figure shows a block diagram for a basic DVS system.

Frequency:
 Dynamic power is directly proportional to frequency, so a chip should not run faster
than necessary.
 Reducing the frequency allows downsizing transistors or using a lower supply voltage.

Low Power Architecture

 Device Level
 Low Capacitance in device and Multi Threshold Devices
 DVFS – Dynamic Voltage Frequency Scaling
 Multi VDD
 Gate Sizing
 Voltage Islands
 Power Gating
 Clock Gating
 Parallelism and Pipelined micro-architecture
Parallel Computations
• Multiple cores
• Multiple Issue pipelines
• Linear power increase
Pipelining
• Faster clock
• Exponential power increase
• Longer branch miss-predictions
2.17.2 : Static power:
 Static power is consumed even when a chip is not switching.
 Static CMOS gates have no contention current.
2.17.2.1 :Sources of static power dissipation:
 Static dissipation due to
 Subthreshold leakage through OFF transistors.
 Gate leakage through gate dielectric.
 Junction leakage from source/drain diffusions.
 Contention current in ratioed circuits.
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 EC3552-VLSI AND CHIP DESIGN
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Pstatic  (Isub  Igate  I junc  Icontention )VDD

1. Subthreshold leakage current:

 Subthreshold leakage current flows when a transistor is OFF.
 Subthreshold leakage current equation is

where Ioff is the subthreshold current at Vgs = 0 and Vds = VDD, and S is the subthreshold
slope.

2. Gate leakage:
 Gate leakage occurs when carriers tunnel through a thin gate dielectric, when a voltage is
applied across the gate (e.g., when the gate is ON).
 Gate leakage is a strong function of the dielectric thickness.
3. Junction leakage:
 Junction leakage occurs when a source or drain diffusion region is at a different potential
from the substrate.
 Leakage of reverse-biased diodes is usually negligible.
4. Contention current:
 Static CMOS circuits have no contention current. However, certain alternative
circuits inherently draw current even while quiescent.
2.17.2.2:Methods of reducing static power:
Power gating:
 To reduce static current during sleep mode is, to turn OFF the power supply to the
sleeping blocks. This technique is called power gating.

 The logic block receives its power from a virtual VDD rail, VDDV.
 When the block is active, the header switch transistors are ON, connecting VDDV to
VDD.
 When the block goes to sleep, the header switch turns OFF, allowing V DDV to float and
gradually sink toward 0.
Multiple threshold voltage and oxide thickness:
 Selective application of multiple threshold voltages can maintain performance on
critical paths with low-Vt transistors, while reducing leakage on other paths with high-
Vt transistors.

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Variable threshold voltage:

 Method to achieve high Ion in active mode and low Ioff in sleep mode is, by adjusting
the threshold voltage of the transistor by applying a body bias.
 This technique is sometimes called variable threshold CMOS (VTCMOS).
 Figure shows a schematic of an inverter using body bias.

**********************************************************************
 Let A, B, C and D be the inputs of a data selector and S0 & S1 be the select lines. Realize a
4:1 data selector using nMOS pass transistor and transmission gate approach. Compare
the hardware complexity. (April 2019-13M)

4:1 MUX using pass transistor

Need double of transistors to design 4:1 MUX using transmission gate compare with pass transistor.

 Realize a 2-input XOR using static CMOS, transmission gate and

dynamic CMOS logic. Analyze the hardware complexity. (April 2019-
15M)
Draw a static CMOS XOR gate. [Nov 2019]

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2-input XOR using static CMOS

2-input XOR using transmission gate

2-input XOR using dynamic CMOS logic

***********************************************************************
Example:
Suppose we wish to implement the two logic functions given by F=A+B+C andG=A+B+C+D.
Assume both true and complementary signals are available. Implement these functions in
dynamic CMOS as cascaded stages so as to minimize the total transistor count. [Nov 2019]
Solution:
Dynamic gates with NMOS pull-down networks cannot be directly cascaded. This solution uses
a domino logic approach.
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Q:What logic function does the circuit implement? To which logic family does the circuit
belong? Does the circuit have any advantages over fully complementary CMOS? [Nov 2019]

Solution:
 The circuit implements Out = (A+BC)’. It is in the pseudo NMOS family.
 The circuit uses less area than a fully complementary CMOS implementation.

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Q:Consider the circuit of Figure [Nov 2019]

What is the logic function implemented by the CMOS transistor network? Size the NMOS and
PMOS devices so that the output resistance is the same as that of an inverter with an NMOS
W/L = 4 and PMOS W/L = 8.

Solution:
The logic function is: Y = [(A+B) CD]’. The transistor sizes are given in the figure above.

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TWO MARK QUESTIONS & ANSWERS

UNIT II - COMBINATIONAL LOGIC CIRCUITS
1. Define combinational circuit and give an example.
A combinational circuit can be defined as a circuit, whose output is dependent only on the
inputs. Example: full adder.

2. Define sequential circuit and give an example.

A sequential circuit can be defined as a circuit, whose output depends not only on the present
value of its inputs but on the sequence of past inputs. Example: flip-flop.

3. What is the static CMOS inverter?

Static CMOS inverter circuit is the combination of nMOS pulldown and pMOS pullup
network.

Figure: Static CMOS inverter

4. What are the advantages of static CMOS circuits?

Advantages of static CMOS circuits:
 Static CMOS circuits have good noise margins
 Static CMOS circuits are fast, low power, easy to design.
 Static CMOS circuits are widely supported by CAD tools,
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 Static CMOS circuits are available in standard cell libraries.

5. What are the disadvantages of static CMOS circuits?

Disadvantages of static CMOS circuits:
 It requires both nMOS and pMOS transistor on each input.
 It has large logical effort.
 Gate delay is increased.

6. What is bubble pushing? (May 2010)

DeMorgan’s law :
A.B  A 
BAB
A.B

Figure: Bubble pushing with DeMorgan’s law

 A NAND gate is equivalent to an OR of inverted inputs.
 A NOR gate is equivalent to an AND of inverted inputs.
 The same relationship applies to gates with more inputs.
 Switching between these representations is easy and is often called bubble pushing.

7. What is meant by compound gate?

Static CMOS efficiently handles compound gates computing various inverting combinations
of AND/OR functions in a single stage.

8. What is the function of skewed gate?

One input transition is more important than the other. HI-skew gates to favor the rising output
transition and LO-skew gates to favor the falling output transition.

9. What are the types of skewed gate?

Two types of skewed gate are HI-skew gate and LO-skew gate.

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10. Define P/N ratio.

P/N ratio is defined as the ratio of pMOS to nMOS transistor width. For processes, a
mobility ratio of µn/µp = 2.

11. What is meant by ratioed logic?

In ratioed logic, a gate consists of an nMOS pull-down network that realizes the logic function
and a simple load device, which replace the entire pull-up network.

12. What is meant by pseudo nMOS logic?

A pseudo nMOS logic (ratioed logic) which uses a grounded pMOS load is referred to as a
pseudo nMOS gate.

13. Draw a pseudo nMOS inverter.(Nov 2011)

Figure: Pseudo nMOS inverter

14. What are the disadvantages of using a pseudo nMOS gate instead of a full
CMOS gate?(May 2012)
What is the drawback of pseudo nMOS logic?
 Pseudo-nMOS gates will not operate correctly if (Maximum low level output) VOL
>VIL (Maximum low level input) of the receiving gate.
 Ratioed circuits dissipate power continually in certain states and have poor
noise margin.
 Ratioed circuits used in situations where smaller area is needed.

15. What are advantages and disadvantages of ratioed logic?

Advantage: Stronger static loads produce faster rising outputs.
Disadvantages:
a. Degrade the noise margin and burn more static power when the output is 0.
b. A resistor is a simple static load, but large resistors consume a large layout area
in typical MOS processes.

16. Compare CMOS combinational logic gates with reference to the equivalent nMOS
depletion load logic with reference to the area requirement.(May 2012)
For CMOS, the area required is 533µm2, for pseudo nMOS the area required is 288 µm2

17. What is AOI logic function?

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AND OR Invert logic function (AOI) implements operation in the order of AND, OR, NOT
operations. So this logic function is known as AOI logic function.
18. What is AOI 221 Gate?
AOI 221, here 221 refers to number of inputs in each section.

19. What is meant by Asymmetric Gates?

When one input is far less critical than another, even nominally symmetric gates can be
made asymmetric to favor the late input at the expense of the early one.

20. What is meant by Cascode Voltage Switch Logic?

Cascode Voltage Switch Logic (CVSL) seeks the benefits of ratioed circuits without
the static power consumption.
It uses both true and complementary input signals and computes both true and
complementary outputs using a pair of nMOS pulldown networks.

21. What are the advantages of Cascode Voltage Switch Logic?

State the reasons for the speed advantages of CVSL family. (Nov 2012)
Advantage: CVSL has a potential speed advantage because all of the logic is performed
with nMOS transistors, thus reducing the input capacitance.

22. Define rise & fall time. [April 2008, Nov/Dec-2008] [Nov/Dec-2009]
Rise time (tr):
 It is defined as time for a waveform to rise from 20% to 80% of its steady state
value. Fall time (tf):
 It is defined as time for a waveform to fall from 80% to 20% of its steady-state value.
23. What is edge rate?
Edge rate is defined as an average value of rise time and fall time.
Edge rate (trf ) = (tr + tf )/2 .

24. What do you mean by propagation delay time?

Propagation delay time (tpd) (or) Maximum delay is defined as maximum time from
the input crossing 50% to the output crossing 50%.

25. What do you mean by contamination delay time?

Contamination delay time (tcd) (or) Minimum delay is defined as minimum time from
the input crossing 50% to the output crossing 50%.

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26. What is meant by average contamination delay time?

Average contamination delay time (tcd) is defined as an average value of rising
contamination delay time (tcdr) and falling contamination delay time (tcdf).
Contamination delay time (tcd) = (tcdr + tcdf)/2
27. What is meant by RC delay model?
RC delay model approximates the nonlinear transistor I-V and C-V characteristics
with an average resistance and capacitance over the switching range of the gate.

28. Draw equivalent RC delay model for a MOS transistor?

Equivalent RC delay model for an nMOS and pMOS transistor:
d
s kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC
s kC
kC
s
d
nMOS transistor pMOS transistor

29. Define electrical or fanout.

Electrical effort is defined as ratio of the output capacitance to input capacitance of
a gate.
Electrical effort (h) = Cout / Cin
30. What is parasitic delay?
The parasitic delay (P) of a gate is the delay of the gate when it drives zero load. It can be
estimated with RC delay models.

31. Write the general expression of parasitic delay for n inputs NAND and NOR
gate?
Expression of parasitic delay for n inputs NAND and NOR is n. Where, n – no. of
inputs.

32. Write the expression for the logical effort and parasitic delay of n input NOR gate.
[Nov/Dec-2011]
Logical effort for n inputs NOR gate is (2n+1)/3
Parasitic delay for n inputs NOR gate is n

33. What is meant by dynamic logic?

 Dynamic logic using a clocked pullup transistor rather than a pMOS that is always ON.

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Figure: Dynamic logic

34. What are the two modes of operation in dynamic logic and give its functions? (NOV
2021)
Dynamic circuit operation has two modes, as shown in Figure.
(i) During precharge, the clock ф is 0, so the clocked pMOS is ON and output Y is high.
(ii) During evaluation, the clock is 1 and the clocked pMOS turns OFF. The output
may remain high or may be discharged low through the pulldown network.

Figure: Precharge and evaluation of dynamic gates

35. What are the disadvantages of dynamic logic?

Disadvantages of dynamic logic:
 Dynamic circuits require careful clocking.
 Dynamic circuits consumes significant dynamic power.
 Dynamic circuits are sensitive to noise during evaluation mode.
 Monotonicity problem
 Dynamic circuits suffer from charge leakage.

36. What are the advantages of dynamic logic?

Advantages of dynamic logic:
 Dynamic circuit has lower input capacitance and no contention during switching.
 Zero static power dissipation.

37. What is the use of footed transistor in dynamic logic circuit?

An extra clocked evaluation transistor can be added to the bottom of the nMOS stack to avoid
contention as shown in the below figure. The extra transistor is called a foot.

Figure: Footed dynamic inverter

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38. What is meant by Monotonicity problem?

 During precharge, the output is pulled HIGH. When the clock rises, the input is HIGH, so
the output is discharged LOW through the pulldown network. The input later falls LOW,
turning OFF the pulldown network.
 However, the precharge transistor is also OFF, so the output floats, staying LOW rather
than rising. This is called monotonicity problem in dynamic circuit.

Figure: Monotonicity problem

39. What is meant by domino logic?

The monotonicity problem can be solved by placing a static CMOS inverter between
dynamic gates. This converts the monotonically falling output into a monotonically rising
signal. The dynamic-static pair together is called domino logic.

40. Write the features of CMOS Domino Logic?

Features of CMOS Domino Logic:
 These structures occupy small area.
 Each gate can make one ‘logic 1’ to ‘logic 0’ transition.

41. What is the use of keeper circuit?

The keeper is a weak transistor that holds or staticizes the output at the correct level when it
floats.

42. What is meant by pass transistors?

In pass-transistor circuits, inputs are applied to the source/drain diffusion terminals.
A single nMOS or pMOS pass transistor suffers from a threshold drop.

43. Which MOS can pass logic 1 and logic 0 strongly?

p-MOS can pass strong logic
1. n-MOS can pass strong
logic 0.

44. What is meant by CMOS Transmission gate? (Nov 2007, May 2011)(or)
Define Transmission gate. (May 2009)
A parallel pair of nMOS and pMOS transistors is called transmission gate.
Transmission gates solve the threshold drop problem but require two transistors in parallel.

45. State the advantages of Transmission gate. (April 2017, May 2021)
Transmission gates solve the threshold drop problem.
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It provides good conducting path between input and output.

46. Draw the CMOS implementation of 4-to-1 MUX using transmission gates.[Nov/Dec
2022]
CMOS implementation of 4-to-1 MUX using transmission gates:

47. What are the various forms of inverter based CMOS logic?
Various forms of inverter based CMOS logic:
i. Pseudo nMOS logic
ii. Dynamic CMOS logic
iii. Clocked CMOS logic
iv. CMOS domino logic

48. Draw 2:1 MUX using transmission gate. (Nov 2008, APRIL-2015, 2016)[April/May 2023]
2:1 MUX using transmission gate:

49. Draw XOR and XNOR using transmission gates. [Apr/may-2010]

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50. Draw a two input XOR using nMOS pass transistor logic. April 2019

51. Define power dissipation. [Nov/Dec-2013]

Power dissipation is defined as power consumed by the transistor unnecessarily, therefore
increasing the power requirement to the logic.

52. List the types of power dissipation. [APRIL 2015, April 2018, Nov 2017]
List the various power losses in CMOS circuits. (May 2013)
Types of power dissipation are static and dynamic power dissipation.

53. What do you understand by static & dynamic power dissipation?

State the various types of power dissipation. (April 2019)
 Dynamic power dissipation is power consumed by transistor when it operates.

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 At some stage both transistor pMOS and nMOS are in ON stage which, leads to
short circuit formation between VDD and GND, thus unwanted power dissipation
occurs.
 Static power dissipation is power consumed by transistor when it is not in
operating stage.

54. What do you mean by low power design?

When both static and dynamic powers are reduced then, the circuit is said to be low
power designed circuit.

55. What are the factors that cause dynamic power dissipation in CMOS
circuits? (Nov 2016, NOV 2021)
Dynamic dissipation due to
 Charging and discharging load capacitances as gates switch.
 “Short-circuit” current while both pMOS and nMOS stacks are partially ON.
56. How can dynamic power dissipation reduced? (or)
State any two criteria for low power logic design. (Nov 2015, MAY 2014)
Dynamic power dissipation (Pdynamic) expressed as below,
P  αCV 2
f
dynamic DD

To reduce dynamic power, use the following

– α: clock gating, sleep mode
– C: small transistors (esp.on clock) short wires.
– VDD: lowest suitable voltage
– f: lowest suitable frequency

57. Write the expression for power dissipation in CMOS inverter. [Nov/Dec-2008]
Total power dissipation Ptotal is the sum of dynamic power dissipation (Pdynamic) and static
power dissipation (Pstatic).

Ptotal = Pdynamic + Pstatic

Where,
P  αCV 2
f
dynamic DD

– α:activity factor
– C: capacitor
– VDD: Supply voltage
– f: Supply frequency
Pstatic  (Isub  Igate  I junc  Icontention )VDD
58. What are the factors that cause static power dissipation in CMOS circuits? [Nov-2012]
List the sources of static power consumption. (Nov 2016, NOV 2021)
Static dissipation due to
 Subthreshold leakage through OFF transistors
 Gate leakage through gate dielectric
 Junction leakage from source/drain diffusion
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 Contention current in ratioed circuits

59. How can static power dissipation reduced?

To reduce static power
– Selectively use ratioed circuits
– Selectively use low Vt devices
– Leakage reduction: Use stacked devices, body bias and low temperature

60. What is Complementary Pass Transistor logic? (NOV/DEC-2014)

Complementary Pass Transistor logic has complementary data inputs and outputs.
It reduces the count of transistors used to make different logic gates, by eliminating
redundant transistors.

61. Implement a 2:1 multiplexer using pass transistor. (NOV/DEC-2013, April 2015)

62. Compare static and dynamic power dissipation. [Nov 2019]

 Static power is power consumed while there is no circuit activity. For example, the
power consumed by a D flip-flop when neither the clock nor the D input have active
inputs (i.e., all inputs are "static" because they are at fixed dc levels).
 Dynamic power is power consumed while the inputs are active. When inputs have ac
activity, capacitors are charging and discharging and the power increases as a result.
The dynamic power includes both the ac component as well as the static component.

63. What is the value of Vout for the figure shown below, where Vtn is threshold voltage of
transistor? (Nov 2016)

Output voltage, Vout = VDD-2Vtn, Where Vtn : Threshold voltage

64. How does a transmission gate produce fully restored logic output? (NOV 2021)
A transmission gate is parallel pairs of nMOS and pMOS transistor. A single nMOS or pMOS
pass transistor suffers from a threshold drop. Transmission gates solve the threshold drop but
require two transistors in parallel.
One of the transistors is passing the value well and the other is passing it poorly. A logic-1 is
passed well through the pMOS but poorly through the nMOS. A logic-0 is passed well
through the nMOS but poorly through the pMOS.

65. What is charge sharing in dynamic CMOS logic[Nov/Dec-2022]

Charge sharing problem occurs when the charge which is stored at the output node in the pre-
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charge phase is shared among the junction capacitance of transistor in the evaluation phase.
Charge sharing may degrade the output voltage level or even cause an erroneous output value.

66. What is use of transmission gates? [April/May-2022]., [Nov/Dec-2020 & April/May-

2021] Used as a
 Logic structure
 Switch
 Latch
 Used solution to deal with the voltage-drop problem.
 Complex gates can be implemented using minimum number of transistors, which also
reduces parasitics.

67. List the sources of power dissipation in CMOS circuits. [April/May-

2022] Static CMOS design:
 Bubble Pushing
 Compound gates
 Skewed gates
Dynamic CMOS design:
 Dual rail domino logic
 Multiple output domino logic

******************************************************************************

Design a half adder using static CMOS logic. [Nov/Dec 2022]

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Design a 4:1 MUX using 2:1 MUX. Realize it using transmission gate. [Nov/Dec 2022]

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Fig: Transmission gate of 4:1 MUX using 2:1 MUX

Realize a 2-input NOR gate, NAND gate, XOR gate, XNOR gate using static CMOS logic.[Apr/May
2022]

Realize a 2-input NOR gate using static CMOS logic, Domino logic and Complementary pass
transistor logic. Analyze the hardware complexity in terms of transistor count. [Nov/Dec 2022]

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Sketch a combinational function Y=(AB+CD)’.

(i) Pseudo-nMOS logic
(ii) Domino logic
(iii) Cascode voltage switch logic. [Nov/Dec 2022] [April / May

2023] Pseudo-nMOS logic

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Domino logic

Cascode voltage switch logic

68. List out the advantages and disadvantages of Pass Transistor Logic. [April/May 2023] The
advantages of pass-transistor logic are the simple design, the reuse of already available signals,
and the low contribution to static power.
The disadvantage of PTL is that the output voltage is lower than the input and it does not
allow series connection of a large number of transistors.

69. List any two types of layout design rules. (Nov 2008, Nov 2009, May 2010)
Two types of layout design rules:
a. Lambda design rules
b. Micron rules

70. What are design rules?

What is the need for design rules? (NOV.2014)
Design rules are a set of geometrical specifications that dictate the design of the layout masks.

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Design rules are used to produce workable mask layouts from which the various layers in
silicon will be formed or patterned.

71. Define the lambda layout rules. (May 2013)

What is meant by lambda layout design rules?
Discuss any two layout design rules. (MAY 2014, APRIL2015, Nov 2015, Nov 2008,
Nov 2009, May 2010)
Lambda-based rules are round up dimensions of scaling to an integer multiple of
scalable parameter λ. Lambda rules make scaling layout as small. The same layout can be
moved to a new process by specifying a new value of λ.
Micron rules can result in as much as a 50% size reduction over lambda rules. Industry
usually uses the micron design rules for layouts.

72. By what factor, gate capacitance must be scaled if constant electric field scaling is
employed? (April 2019)
Gate capacitance is scaled by scaling factor in constant electric field scaling.
1
S
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73. What are stick diagrams?
Stick diagrams are used to convey layer information through the use of a color code. A stick
diagram is a cartoon of a chip layout. The stick diagram represents the rectangles with lines
which represent wires and component symbols.

74. What are the uses of Stick diagram?

Uses of stick diagram:
 It can be drawn much easier and a faster than complex layout.
 These are especially important tools for layout built from large cells.

75. Give the various color coding used in stick diagram?

Various color coding used in stick diagram:
 Green – n-diffusion, Red- polysilicon, Blue –metal, Yellow- implant
and Black-contact areas.

76. Why does interconnect increase the circuit delay? [Nov/Dec-2011]

Interconnect is defined by its resistance value and capacitance with neighbor. Delay is
calculated from resistance and capacitance value.

77. What is transistor sizing problem?(MAY 2014)

Transistor sizing is carried out by equating the maximum on resistances of the logic
circuit with inverter one.

78. What is the need of demarcation line? (Nov 2017)

In CMOS, a demarcation line is drawn to avoid touching of p-diff with n-diff. All
pMOS must lie on one side of the line and all nMOS must lie on other side.
79. Draw the stick diagram and layout for CMOS inverter. (Nov 2016)
Stick diagram Layout diagaram

80. Draw the stick diagram of static CMOS 2-input NAND gate. (April 2018)

81. What are simulations available for VLSI circuits?

In VLSI the following simulations are available
 Path simulation, Monte Carlo simulation and Interconnect simulation

82. Why nMOS transistor is selected as pull down network? (Nov 2017)
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Pull-up and pull-down networks in CMOS circuits are never both conducting and are
never both opened at the same time. This is the reason that nMOS transistors are used in the
pull-down network and pMOS in the pull-up network of a CMOS gate.

83. Draw the stick diagram of NMOS NOR gate. [Nov 2019]

84. How do you describe the term device modeling? [May/June-2013]

The device modeling describes how to model diffusion capacitance and how to run
simulations in various process corners.

85. What is Elmore’s delay model? (or) Give the expression for Elmore delay and state the
various parameters associated with it. (NOV. 2014, April 2016, 2017, 2018, Nov 2017)
[April/May – 2023]
The Elmore delay model estimates the delay from a source switching to one of the
leaf nodes. Delay is summing over each node i of the capacitance Ci on the node multiplied
by the effective resistance R.
Propagation delay time:
tpd  RitosourceCi

 nodes
i
 R1C1  R1  R2 C2 ...  R1  R2 ...  RN CN
RC delay equivalent for series of transistors:
R1 R2 R3 RN

C1 C2 C3 CN

86. Define logical effort and give logical effort value of inverter.
Logical effort (g) is defined as the ratio of the input capacitance of a gate to the input
capacitance of an inverter delivering the same output current.
An inverter has a logical effort of 1.

87. Write the general expression of logical effort for n inputs NAND and NOR
gate?
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Expression of logical effort for n inputs NAND is (n+2)/3.
Expression of logical effort for n inputs NOR is (2n+1)/3. Where, n – no. of inputs.

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88. Draw a 2- input CMOS NOR Gate. [Nov/Dec-2022]

89. Write the expression for parasitic delay and logical effort of an N-input NAND gate.
[April/May-2022]
Solution :
Parasitic delay for N-input NAND gate = n
Logical effort of an N-input NAND gate =
(n+2)/3
90. Sketch a complementary CMOS gate computing W = (XY+YZ)’. [April/May-2022]
Sketch a complementary CMOS gate computing Y = (AB+BC)’. [Nov/Dec-2020,
April/May-2021]

91. What is body effect. [Nov/Dec-2020, April/May-2021]

Vt is not constant with respected to voltage difference between substrate and source of MOS
transistor. This is known as body effect. Its other name is substrate-bias effect.

92. What is velocity saturation effect?

The velocity of charge carriers is linearly proportional to the eclectic field and the
proportionally constant mobility of carrier.
When we increase the electric field beyond certain velocity called as the thermal velocity
or saturation velocity.
Electron attains in the presence of very high electric fields.
At high electric field carriers fail to follow this linear model.

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93. Define propagation delay of a CMOS inverter.

It expresses the delay experienced by a signal when passing through a gate. It is measured
between the 50% transition points of the input and output waveforms, as shown in Figure for
an inverting gate. Because a gate displays different response times for rising or falling input
waveforms, two definitions of the propagation delay are necessary. The tpLH defines the
response time of the gate for a low to high (or positive) output transition, while tpHL refers to
a high to low (or negative) transition. The propagation delay tp is defined as the average of
the two.

94. Why NMOS device conducts strong zero and weak

one? Reason:
• Greater switching speed.
• Weak transistor is used to generate a high output voltage level
• The gate is “high” and channel is ‘low’.
• Nmos is turn on. Vg is at VDD VS charging towards VDD.

95. What is Intrinsic and Extrinsic Semiconductor?

The pure Silicon is known as Intrinsic Semiconductor. When impurity is added with pure
Silicon, its electrical properties are varied. This is known as Extrinsic Semiconductor.

96. State the channel length modulation. Write the equation for describing channel length
modulation effect in NMOS transistor.
Channel length is varied due to changes in Vds (drain to source voltage). In saturation region,
channel length is decreased when (W/L) ratio is increased. So ᵝ is increased and drain voltage
is increased.

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97. What is latch up? How is Prevent latch up?

Latch up is the condition occurs in the circuit manufactured using bulk
CMOS technology. When IC is the state of “Latch Up”.
Latch Up Prevention in two ways:
• Latch up resistant CMOS processes
• Layout technique.

98. What are the different MOS layers?

• n-diffusion
• p-diffusion
• Polysilicon
• Metal

99. If two CMOS inverters are cascaded with an aspect ratio of 1:1
then determine the inverter pair delay. [Nov/Dec-2022]

Solution :
Logical Effort of the inverter , g = 1
Here, single identical load. So, the electrical
effort , h =1 Parasitic delay of an inverter , Pinv
=1
Then, the delay of each stage is expressed as,
d = gh + p

= 1(1)+1
=2