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Practice Set - 07 (Fathom)

The document contains a practice set focused on computer organization and architecture, specifically addressing instruction formats and various addressing modes. It includes questions regarding memory units, instruction execution, and effective address calculations for different addressing modes. Solutions are required for each question, emphasizing understanding of memory addressing and instruction execution processes.

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2024.cs1g.ayushkapal2412720
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18 views2 pages

Practice Set - 07 (Fathom)

The document contains a practice set focused on computer organization and architecture, specifically addressing instruction formats and various addressing modes. It includes questions regarding memory units, instruction execution, and effective address calculations for different addressing modes. Solutions are required for each question, emphasizing understanding of memory addressing and instruction execution processes.

Uploaded by

2024.cs1g.ayushkapal2412720
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Computer Organization and Architecture

Practice Set - 07

Q1 (*MM8-13). The memory unit of a computer has 256K words of 32 bits each. The computer has an
instruction format with four fields: an operation code field, a mode field to specify one of seven
addressing modes, a register address field to specify one of 60 processor registers, and a memory
address. Specify the instruction format and the number of bits in each field if the in instruction is in one
memory word.

Solution:

Q2 (*MM8-14). A two-word instruction is stored in memory at an address designated by the symbol W.


The address field of the instruction (stored at W + 1) is designated by the symbol Y. The operand used
during the execution of the instruction is stored at an address symbolized by Z. An index register
contains the value X. State how Z is calculated from the other addresses if the addressing mode of the
instruction is:
a. direct b. indirect c. relative d. indexed

Solution:

Q3 (*MM8-15). A relative mode branch type of instruction is stored in memory at an address equivalent
to decimal 750. The branch is made to an address equivalent to decimal 500.

a. What should be the value of the relative address field of the instruction (in decimal)?

b. Determine the relative address value in binary using 12 bits. (Why must the number be in 2's
complement?)
c. Determine the binary value in PC after the fetch phase and calculate the binary value of 500. Then
show that the binary value in PC plus the relative address calculated in part (b) is equal to the binary
value of 500.

Solution:

Q4 (*MM8-16). How many times does the control unit refer to memory when it fetches and executes an
indirect addressing mode instruction if the instruction is:
(a) a computational type requiring an operand from memory; (b) a branch type.

Solution:

Q5 (*MM8-17). What must the address field of an indexed addressing mode instruction be to make it
the same as a register indirect mode instruction?

Solution:
The address part of the indexed mode instruction must be set to zero.

Q6 (*MM8-18). An instruction is stored at location 300 with its address field at location 301. The
address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective
address if the addressing mode of the instruction is-

(a) direct; (b) immediate; (c) relative; (d) register indirect; (e) indexed with R1 as the index register.

Solution:

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