2.

Precautions in use of LCD Modules

(1)Avoid applying excessive shocks to the module or making any alterations or modifications to it.
(2)Dont make extra holes on the printed circuit board, modify its shape or change the components of
LCD module.
(3)Dont disassemble the LCM.
(4)Dont operate it above the absolute maximum rating.
(5)Dont drop, bend or twist LCM.
(6)Soldering: only to the I/O terminals.
(7)Storage: please storage in anti-static electricity container and clean environment.

3.General Specification

Item Dimension Unit

Number of Characters 20 characters x 4Lines

Module dimension 98.0 x 60.0 x 13.6(MAX) mm

View area 77.0 x 25.2 mm

Active area 70.4 x 20.8 mm

Dot size 0.55 x 0.55 mm

Dot pitch 0.60 x 0.60 mm

Character size 2.95 x 4.75 mm

Character pitch 3.55 x 5.35 mm

LCD type STN, Negative, Transmissive, Blue

Duty 1/16

View direction 6 oclock

Backlight Type LED ,White

5 28
4.Absolute Maximum Ratings

Item Symbol Min Typ Max Unit

Operating Temperature TOP -20 70

Storage Temperature TST -30 80

Input Voltage VI VSS VDD V

Supply Voltage For Logic VDD-VSS -0.3 7 V

Supply Voltage For LCD VDD-V0 -0.3 13 V

5.Electrical Characteristics

Item Symbol Condition Min Typ Max Unit

Supply Voltage For

VDD-VSS 4.5 5.0 5.5 V
Logic

Ta=-20 5.3 V
Supply Voltage For
VDD-V0 Ta=25 4.5 V
LCD
Ta=70 3.8 V

Input High Volt. VIH 0.7 VDD VDD V

Input Low Volt. VIL VSS 0.6 V

Output High Volt. VOH 3.9 V

Output Low Volt. VOL 0.4 V

Supply Current IDD VDD=5.0V 1.0 1.2 1.5 mA

6 28
6.Optical Characteristics

Item Symbol Condition Min Typ Max Unit

(V) CR2 20 40 deg

View Angle
(H) CR2 -30 30 deg

Contrast Ratio CR 3

T rise 150 200 ms

Response Time
T fall 150 200 ms

Definition of Operation Voltage (Vop) Definition of Response Time ( Tr , Tf )

Non-selected Non-selected
Conition Selected Conition Conition
Intensity Selected Wave
100 Non-selected Wave Intensity

10
Cr Max
Cr = Lon / Loff 90
100

Vop
Driving Voltage(V) Tr Tf

[positive type] [positive type]

Conditions :
Operating Voltage : Vop Viewing Angle() : 0 0
Frame Frequency : 64 HZ Driving Waveform : 1/N duty , 1/a bias

Definition of viewing angle(CR2)

b
f
= 180
l
r

= 270 = 90

= 0
7 28
7.Interface Pin Function

Pin No. Symbol Level Description

1 VSS 0V Ground

2 VDD 5.0V Supply Voltage for logic

3 VO (Variable) Operating voltage for LCD

4 RS H/L H: DATA, L: Instruction code

5 R/W H/L H: Read(MPUModule) L: Write(MPUModule)

6 E H,HL Chip enable signal

7 DB0 H/L Data bus line

8 DB1 H/L Data bus line

9 DB2 H/L Data bus line

10 DB3 H/L Data bus line

11 DB4 H/L Data bus line

12 DB5 H/L Data bus line

13 DB6 H/L Data bus line

14 DB7 H/L Data bus line

15 A Power supply for B/L(+)/Negative Voltage output

16 K Power supply for B/L(-)

8 28
8.Contour Drawing &Block Diagram

98.0 0.5
0.6 96.8
10.5 77.0(VA)
1 V ss
13.8 70.4(AA)
2 V dd
10.0 P2.54*15=38.06 13.6 MAX 9.3 MAX
3 Vo

2.5

2.5
2.0 9.0 4.7
4 RS
5 R/W
10.35
17.4
19.6

1 16- 1.0 PTH 16

6 E
7 D B0
8 D B1
25.2(VA)
20.8(AA)
60.0 0.5

9 D B2
39.3

55.0
10 D B3
11 D B4
12 D B5
13 D B6
14 D B7
49.0 4- 2.5 PTH 1.6 1.6 15 A
2.5 93.0 4- 5.0 PAD 16 K
LED B /L EL or N O B/L

2.95 0.6
0.6
0.55

The non-specified tolerance of dimension is 0.3mm.

0.6
0.55
4.75
0.6

D O T SIZE

RS C om1~16
R /W C ontroller/C om Driver
M PU
E H D44780
D B0~DB7 or
C om 17~32
20X4 LCD
80 series Equivalent
or
68 series
Power Circuit

Seg1~ 40
V dd Seg41~120 Seg120~200
D
Bias and

VR Vo
Seg D river Seg D river
10K~20K Vss

M
C L1
Generator

C L2
Vee
N.V.

V dd,V ss,V 1~V5

External contrast adjustment.
O ptional

Character located 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
D DRA M address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
D DRA M address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
D DRA M address 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27
D DRA M address 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67

9 28
9.Function Description

The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an
instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for
display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the
MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When
address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM.
By the register selector (RS) signal, these two registers can be selected.

RS R/W Operation

0 0 IR write as an internal operation (display clear, etc.)

0 1 Read busy flag (DB7) and address counter (DB0 to DB7)

1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)

1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)

Busy Flag (BF)

When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction
will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. The next instruction
must be written after ensuring that the busy flag is 0.

Address Counter (AC)

The address counter (AC) assigns addresses to both DDRAM and CGRAM

Display Data RAM (DDRAM)

This DDRAM is used to store the display data represented in 8-bit character codes. Its extended
capacity is 808 bits or 80 characters. Below figure is the relationships between DDRAM addresses
and positions on the liquid crystal display.

High bits Low bits

Example: DDRAM addresses 4E

AC
AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0
(hexadecimal)

10 28
 Display position DDRAM address

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27
54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67
4-Line by 20-Character Display

Character Generator ROM (CGROM)

The CGROM generate 58 dot or 510 dot character patterns from 8-bit character codes. See Table 2.

Character Generator RAM (CGRAM)

In CGRAM, the user can rewrite character by program. For 58 dots, eight character patterns can be
written, and for 510 dots, four character patterns can be written.
Write into DDRAM the character code at the addresses shown as the left column of table 1. To show
the character patterns stored in CGRAM.

11 28
Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns

Table 1.

F o r 5 * 8 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s C h a ra c te r P a tte rn s
C G R A M A d d re ss
( D D R A M d a ta ) ( C G R A M d a ta )

7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
H ig h Low H ig h Low H ig h Low
0 0 0 * * * 0
0 0 1 * * * 0 0 0
0 1 0 * * * 0 0 0
0 1 1 * * * 0 C h a ra c te r
0 0 0 1 0 0 * * * 0 0 0 p a tte rn ( 1 )
0 0 0 0 * 0 0 0
1 0 1 * * * 0 0 0
1 1 0 * * * 0 0 0
1 1 1 * * * 0 0 0 0 0 C u rs o r p a tte rn
0 0 0 * * * 0 0 0
0 0 1 * * * 0 0 0
0 1 0 * * *
0 1 1 * * * 0 0 0 0 C h a ra c te r
0 0 0 0 * 0 0 1 0 0 1 1 0 0 * * * p a tte rn ( 2 )
1 0 1 * * * 0 0 0 0
1 1 0 * * * 0 0 0 0
1 1 1 * * * 0 0 0 0 0 C u rs o r p a tte rn
0 0 0 * * *
0 0 1

0 0 0 0 * 1 1 1 1 1 1 1 0 0
1 0 1
1 1 0
1 1 1 * * *
F o r 5 * 1 0 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s C h a ra c te r P a tte rn s
C G R A M A d d re ss
( D D R A M d a ta ) ( C G R A M d a ta )

7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
H ig h Low H ig h Low H ig h Low
0 0 0 0 * * * 0 0 0 0 0
0 0 0 1 * * * 0 0 0 0 0
0 0 1 0 * * * 0 0
0 0 1 1 * * * 0 0
0 1 0 0 * * * 0 0 0
0 0 0 0 * 0 0 0 0 0 0 1 0 1 * * * 0 0 0
0 1 1 0 * * * 0 C h a ra c te r
0 1 1 1 * * * 0 0 0 0 p a tte rn
1 0 0 0 * * * 0 0 0 0
1 0 0 1 * * * 0 0 0 0
1 0 1 0 * * * 0 0 0 0 0 C u rs o r p a tte rn

1 1 1 1 * * * * * * * *

: " H ig h "

12 28
10.Character Generator ROM Pattern

Table.2
Upper
4 bit
Lower LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH
4 bit
CG
LLLL RAM
(1)
CG
LLLH RAM
(2)
CG
LLHL RAM
(3)
CG
LLHH RAM
(4)
CG
LHLL RAM
(5)
CG
LHLH RAM
(6)
CG
LHHL RAM
(7)
CG
LHHH RAM
(8)
CG
HLLL RAM
(1)
CG
HLLH RAM
(2)
CG
HLHL RAM
(3)
CG
HLHH RAM
(4)
CG
HHLL RAM
(5)
CG
HHLH RAM
(6)
CG
HHHL RAM
(7)
CG
HHHH RAM
(8)

13 28
11.Instruction Table

Instruction Code Execution time

Instruction Description
(fosc=270Khz)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Write 00H to DDRAM and set

Clear Display 0 0 0 0 0 0 0 0 0 1 1.53ms
DDRAM address to 00H from AC

Set DDRAM address to 00H from AC

and return cursor to its original position

Return Home 0 0 0 0 0 0 0 0 1 1.53ms
if shifted. The contents of DDRAM are

not changed.

Entry Mode Assign cursor moving direction and

0 0 0 0 0 0 0 1 I/D SH 39s
Set enable the shift of entire display.

Display
Set display (D), cursor (C), and blinking
ON/OFF 0 0 0 0 0 0 1 D C B 39s
of cursor (B) on/off control bit.
Control

Set cursor moving and display shift

Cursor or
0 0 0 0 0 1 S/C R/L control bit, and the direction, without 39s
Display Shift
changing of DDRAM data.

Set interface data length

(DL:8-bit/4-bit), numbers of display line

Function Set 0 0 0 0 1 DL N F 39s
(N:2-line/1-line)and, display font type

(F:511 dots/58 dots)

Set CGRAM
0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39s
Address

Set DDRAM
0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39s
Address

Whether during internal operation or not

Read Busy
can be known by reading BF. The
Flag and 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 0s
contents of address counter can also be
Address
read.

Write Data to Write data into internal RAM

1 0 D7 D6 D5 D4 D3 D2 D1 D0 43s
RAM (DDRAM/CGRAM).

Read Data Read data from internal RAM

1 1 D7 D6 D5 D4 D3 D2 D1 D0 43s
from RAM (DDRAM/CGRAM).

dont care

14 28
12.Timing Characteristics
12.1 Write Operation

Ta=25, VDD=5.0V

Item Symbol Min Typ Max Unit

Enable cycle time TC 1200 ns

Enable pulse width TPW 140 ns

Enable rise/fall time TR,TF 25 ns

Address set-up time (RS, R/W to E) tAS 0 ns

Address hold time tAH 10 ns

Data set-up time tDSW 40 ns

Data hold time tH 10 ns

15 28
12.2 Read Operation

Ta=25, VDD=5V

Item Symbol Min Typ Max Unit

Enable cycle time TC 1200 ns

Enable pulse width (high level) TPW 140 ns

Enable rise/fall time TR,TF 25 ns

Address set-up time (RS, R/W to E) tAS 0 ns

Address hold time tAH 10 ns

Data delay time tDDR 100 ns

Data hold time tH 10 ns

16 28
13.Initializing of LCM

Power on

Wait for more than 40 ms after VDD rises to 4.5 V

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set
0 0 0 0 1 1 * * * *

Wait for more than 39us

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function set
0 0 0 0 1 0 * * * *
0 0 N F * * * * * *

Wait for more than 39 s

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 * * * * Function set
0 0 N F * * * * * *

Wait for more than 37us

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control
0 0 0 0 0 0 * * * *
0 0 1 D C B * * * *

Wait for more than 37 s

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear
0 0 0 0 0 0 * * * *
0 0 0 0 0 1 * * * *

Wait for more than 1.53ms

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set
0 0 0 0 0 0 * * * *
0 0 0 1 I/D SH * * * *

Initialization ends

4-Bit Ineterface

17 28
 Power on

Wait for more than 40 ms after VDDrises to 4.5 V

BF can not be checked before this instruction.

RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set
0 0 0 0 1 1 N F * *

Wait for more than 39us

BF can not be checked before this instruction.

RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function set
0 0 0 0 1 1 N F * *

Wait for more than 37us

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control
0 0 0 0 0 0 1 B C D

Wait for more than 37 s

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear
0 0 0 0 0 0 0 0 0 1

Wait for more than 1.53ms

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set
0 0 0 0 0 0 0 1 I/D S

Initialization ends

8-Bit Ineterface

18 28
14.Reliability
Content of Reliability Test (wide temperature, -20~70)

Environmental Test
Test Item Content of Test Test Condition Note
High Temperature Endurance test applying the high storage 80
2
storage temperature for a long time. 200hrs
Low Temperature Endurance test applying the high storage -30
1,2
storage temperature for a long time. 200hrs
Endurance test applying the electric stress
High Temperature 70
(Voltage & Current) and the thermal stress to the
Operation 200hrs
element for a long time.
Low Temperature Endurance test applying the electric stress under -20
1
Operation low temperature for a long time. 200hrs
The module should be allowed to stand at 60
,90%RH max
High Temperature/ For 96hrs under no-load condition excluding the 60,90%RH
1,2
Humidity Operation polarizer, 96hrs
Then taking it out and drying it at normal
temperature.
The sample should be allowed stand the
following 10 cycles of
operation
Thermal shock -20 25 70 -20/70

resistance 10 cycles

30min 5min 30min

1 cycle
Total fixed
amplitude : 1.5mm
Vibration
Frequency :
Endurance test applying the vibration during
Vibration test 10~55Hz 3
transportation and using.
One cycle 60
seconds to 3
directions of X,Y,Z
for Each
15 minutes
VS=800V,RS=1.5k
Endurance test applying the electric stress to the
Static electricity test
terminal. CS=100pF
1 time
Note1: No dew condensation to be observed.
Note2: The function test shall be conducted after 4 hours storage at the normal
Temperature and humidity after remove from the test chamber.
Note3: Vibration test will be conducted to the product itself without putting it in a container.

19 28
15.Backlight Information

Specification

PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION

Supply Current ILED 43.2 48 75 mA V=3.5V

Supply Voltage V 3.4 3.5 3.6 V

Reverse Voltage VR 8 V

Luminous
IV 280 350 CD/M2 ILED=48mA
Intensity

Life Time nm ILED=48mA

Color White
Note: The LED of B/L is drive by current only, drive voltage is for reference only.
drive voltage can make driving current under safety area (current between
minimum and maximum).

2.Drive from pin15,pin16

R R
A
B/L
K

LCM
ill never get Vee output from pin15)

20 28