H2004A

LCD MODULE MANUAL

Character 20X4

Contents
1. Precautions in use of LCD Modules

2. General Specification

3. Absolute Maximum Ratings

4. Electrical Characteristics

5. Optical Characteristics

6. Interface Pin Function

7. Contour Drawing & Block Diagram

8. Function Description

9. Character Generator ROM Pattern

10. Instruction Table

11. Timing Characteristics

12. Backlight Information

13. Initializing of LCM

1
1. Precautions in use of LCD Modules

(1)Avoid applying excessive shocks to the module or making any alterations or modifications to it.
(2)Don’t make extra holes on the printed circuit board, modify its shape or change the components
of LCD module.
(3)Don’t disassemble the LCM.
(4)Don’t operate it above the absolute maximum rating.
(5)Don’t drop, bend or twist LCM.
(6)Soldering: only to the I/O terminals.
(7)Storage: please storage in anti-static electricity container and clean environment.

2. General Specification

Item Dimension Unit

Number of Characters 20 characters x 4Lines -
Module dimension 98.0 x 60.0 x 13.6(MAX) mm
View area 77.0 x 25.2 mm
Active area 70.4 x 20.8 mm
Dot size 0.55 x 0.55 mm
Dot pitch 0.60 x 0.60 mm
Character size 2.95 x 4.75 mm
Character pitch 3.55 x 5.35 mm
LCD type STN, Positive
Duty 1/16
View direction 6 o’clock
Backlight Type LED

3. Absolute Maximum Ratings

Item Symbol Min Typ Max Unit

Operating Temperature TOP -20 - +70 -
Storage Temperature TST -30 - +80 -
Input Voltage VI VSS - VDD V
Supply Voltage For Logic VDD-VSS -0.3 - 7 V
Supply Voltage For LCD VDD-V0 -0.3 - 13 V

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4. Electrical Characteristics

Item Symbol Condition Min Typ Max Unit

Supply Voltage For Logic VDD-VSS - 4.5 - 5.5 V
Ta=-20°C - - 5.5 V
Supply Voltage For LCD VDD-V0 Ta=25°C - 4.5 - V
Ta=70°C 3.8 - - V
Input High Volt. VIH - 2.2 - VDD V
Input Low Volt. VIL - - - 0.6 V
Output High Volt. VOH - 2.4 - - V
Output Low Volt. VOL - - - 0.4 V
Supply Current IDD VDD=5V - 1.6 - mA

5. Optical Characteristics

Item Symbol Condition Min Typ Max Unit

(V)θ CR≥2 10 - 105 deg
View Angle
(H)φ CR≥2 -30 - 30 deg

Contrast Ratio CR - - 3 - -

T rise - - 150 200 ms

Response Time
T fall - - 150 200 ms

3
 Definition of Operation Voltage (Vop) Definition of Response Time ( Tr , Tf )

Non-selected Non-selected
Conition Selected Conition Conition
Intensity Selected Wave
100¢ H Non-selected Wave Intensity

10¢ H
Cr Max
Cr = Lon / Loff 90¢ H
100¢ H

Vop
Driving Voltage(V) Tr Tf

[positive type] [positive type]

Conditions :
Operating Voltage : Vop Viewing Angle(θ) : 0°
Frame Frequency : 64 HZ Driving Waveform : 1/N duty , 1/a bias

Definition of viewing angle(CR≥2)

θb
θf
ϕ = 180°X
θl
θr

ϕ = 270°X ϕ = 90°X

ϕ = 0°X

4
6. Interface Pin Function

Pin No. Symbol Level Description

1 VSS 0V Ground
2 VDD 5.0V Supply Voltage for logic
3 VO (Variable) Operating voltage for LCD
4 RS H/L H: DATA, L: Instruction code
5 R/W H/L H: Read(MPU→Module) L: Write(MPU→Module)
6 E H,H→L Chip enable signal

7 DB0 H/L Data bit 0

8 DB1 H/L Data bit 1
9 DB2 H/L Data bit 2
10 DB3 H/L Data bit 3
11 DB4 H/L Data bit 4
12 DB5 H/L Data bit 5
13 DB6 H/L Data bit 6
14 DB7 H/L Data bit 7
15 A 4.2V-4.6V LED +
16 K 0V LED -

5
7. Contour Drawing &Block Diagram

98.0 0.5
0.6 96.8
10.5 77.0(VA) 1 Vss
13.8 70.4(AA)
2 Vdd
10.0 P2.54*15=38.06 13.6 MAX
2.0 9.0
3 Vo

2.5

2.5
4 RS
5 R/W
10.35

1 16- 1.0 PTH 16

17.4
19.6

6 E
7 DB0
8 DB1
60.0 0.5

9 DB2
25.2(VA)
20.8(AA)

55.0
39.3

10 DB3
11 DB4
12 DB5
13 DB6
14 DB7
49.0 4- 2.5 PTH 1.6 15 A
2.5 93.0 4- 5.0 PAD 16 K
LEDB/L

2.95 0.6
0.6
0.55

The non-specified tolerance of dimension is 0.3mm.

0.6
0.55
4.75
0.6

DOT SIZE

RS Com1~16
LEDB/L Drive Method
1.Drive fromA,K
R/W Controller/ComDriver
MPU
E
DB0~DB7
HD44780
or
Com17~32
20X4 LCD R
A
80 series
or Equivalent B/L
K
68 series

Seg1~40 2.Drive from pin15, pin16

Vdd
Power Circuit

Seg41~120 Seg120~200
D
VR Vo
Bias and

Seg Driver Seg Driver R R

10K~20K Vss A
B/L
K
M
CL1
LCM
(Will never get Vee output frompin15)
Generator

CL2
Vee
Vdd,Vss,V1~V5
N.V.

External contrast adjustment.

Optional

Character located 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
DDRAMaddress 00 01 02 03 04 05 06 07 08 09 0A0B0C0D0E 0F 10 11 12 13
DDRAMaddress 40 41 42 43 44 45 46 47 48 49 4A4B4C4D4E 4F 50 51 52 53
DDRAMaddress 14 15 16 17 18 19 1A1B1C1D1E 1F 20 21 22 23 24 25 26 27
DDRAMaddress 54 55 56 57 58 59 5A5B5C5D5E 5F 60 61 62 63 64 65 66 67

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8. Function Description

The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an
instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for
display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from
the MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When
address information is written into the IR, then data is stored into the DR from DDRAM or
CGRAM. By the register selector (RS) signal, these two registers can be selected.

RS R/W Operation
0 0 IR write as an internal operation (display clear, etc.)
0 1 Read busy flag (DB7) and address counter (DB0 to DB7)
1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)
1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)

Busy Flag (BF)

When the busy flag is 1, the controller LSI is in the internal operation mode, and the next
instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. The
next instruction must be written after ensuring that the busy flag is 0.

Address Counter (AC)

The address counter (AC) assigns addresses to both DDRAM and CGRAM

Display Data RAM (DDRAM)

This DDRAM is used to store the display data represented in 8-bit character codes. Its extended
capacity is 80×8 bits or 80 characters. Below figure is the relationships between DDRAM
addresses and positions on the liquid crystal display.

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Character Generator ROM (CGROM)
The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes. See
Table 2.

Character Generator RAM (CGRAM)

In CGRAM, the user can rewrite character by program. For 5×8 dots, eight character patterns can
be written, and for 5×10 dots, four character patterns can be written.
Write into DDRAM the character code at the addresses shown as the left column of table 1. To
show the character patterns stored in CGRAM.

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 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
patterns

Table 1.

F o r 5 * 8 d o t c h a r a c te r p a tte rn s
C h a ra c te r C o d e s C h a ra c te r P a tte rn s
C G R A M A d d ress
( D D R A M d a ta ) ( C G R A M d a ta )

7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
H ig h Low H ig h Low H ig h Low
0 0 0 * * * 0
0 0 1 * * * 0 0 0
0 1 0 * * * 0 0 0
0 1 1 * * * 0 C h a ra c te r
0 0 0 1 0 0 * * * 0 0 0 p a tte rn ( 1 )
0 0 0 0 * 0 0 0
1 0 1 * * * 0 0 0
1 1 0 * * * 0 0 0
1 1 1 * * * 0 0 0 0 0 C u rs o r p a tte r n
0 0 0 * * * 0 0 0
0 0 1 * * * 0 0 0
0 1 0 * * *
0 1 1 * * * 0 0 0 0 C h a ra c te r
0 0 0 0 * 0 0 1 0 0 1 1 0 0 * * * p a tte rn ( 2 )
1 0 1 * * * 0 0 0 0
1 1 0 * * * 0 0 0 0
1 1 1 * * * 0 0 0 0 0 C u rs o r p a tte r n
0 0 0 * * *
0 0 1

0 0 0 0 * 1 1 1 1 1 1 1 0 0
1 0 1
1 1 0
1 1 1 * * *
F o r 5 * 1 0 d o t c h a r a c te r p a tte r n s
C h a ra c te r C o d e s C h a ra c te r P a tte rn s
C G R A M A d d ress
( D D R A M d a ta ) ( C G R A M d a ta )

7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0
H ig h Low H ig h Low H ig h Low
0 0 0 0 * * * 0 0 0 0 0
0 0 0 1 * * * 0 0 0 0 0
0 0 1 0 * * * 0 0
0 0 1 1 * * * 0 0
0 1 0 0 * * * 0 0 0
0 0 0 0 * 0 0 0 0 0 0 1 0 1 * * * 0 0 0
0 1 1 0 * * * 0 C h a ra c te r
0 1 1 1 * * * 0 0 0 0 p a tte rn
1 0 0 0 * * * 0 0 0 0
1 0 0 1 * * * 0 0 0 0
1 0 1 0 * * * 0 0 0 0 0 C u rs o r p a tte r n

1 1 1 1 * * * * * * * *

: " H ig h "

9
9. Character Generator ROM Pattern

Table.2
Upper
4 bit
Lower LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH
4 bit
CG
RAM
LLLL (1)

LLLH (2)

LLHL (3)

LLHH (4)

LHLL (5)

LHLH (6)

LHHL (7)

LHHH (8)

HLLL (1)

HLLH (2)

HLHL (3)

HLHH (4)

HHLL (5)

HHLH (6)

HHHL (7)

HHHH (8)

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10. Instruction Table

Instruction Code
Execution time
Instruction Description
(fosc=270Khz)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Write “00H” to DDRAM and set

Clear Display 0 0 0 0 0 0 0 0 0 1 1.53ms
DDRAM address to “00H” from AC
Set DDRAM address to “00H” from AC
and return cursor to its original position if
Return Home 0 0 0 0 0 0 0 0 1 － 1.53ms
shifted. The contents of DDRAM are not
changed.
Entry Mode Assign cursor moving direction and
0 0 0 0 0 0 0 1 I/D SH 39μs
Set enable the shift of entire display.
Display
Set display (D), cursor (C), and blinking
ON/OFF 0 0 0 0 0 0 1 D C B 39μs
of cursor (B) on/off control bit.
Control
Set cursor moving and display shift
Cursor or
0 0 0 0 0 1 S/C R/L － － control bit, and the direction, without 39μs
Display Shift
changing of DDRAM data.
Set interface data length (DL:8-bit/4-bit),
numbers of display line
Function Set 0 0 0 0 1 DL N F － － 39μs
(N:2-line/1-line)and, display font type
(F:5×11 dots/5×8 dots)
Set CGRAM
0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39μs
Address
Set DDRAM
0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39μs
Address
Whether during internal operation or not
Read Busy
can be known by reading BF. The
Flag and 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 0μs
contents of address counter can also be
Address
read.
Write Data to Write data into internal RAM
1 0 D7 D6 D5 D4 D3 D2 D1 D0 43μs
RAM (DDRAM/CGRAM).
Read Data Read data from internal RAM
1 1 D7 D6 D5 D4 D3 D2 D1 D0 43μs
from RAM (DDRAM/CGRAM).

I/D = 1 : Increment C=1 : Cursor ON R/L = 1 : Right Shift F = 0 : 5x7 Dots

I/D = 0 : Decrement C=0 : Cursor OFF R/L = 0 : Left Shift F = 1 : 5x10 Dots

S=1 : Display shift B=1 : Blink ON DL = 1 : 8 Bits BF = 1 : Busy

S=0 : No display shift B=0 : Blink OFF DL = 0 : 4 Bits BF = 0 : Can Accept Data

D=1 : Display ON S/C = 1 : Display Shift N = 1 : 2 Lines ACG : CG RAM Address

D=0 : Display OFF S/C = 0 : Cursor Move N = 0 : 1 Line ADD : DD RAM Address

* : don't care

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11. Timing Characteristics
11.1 Write Operation

VIH1 VIH1
RS VIL1 VIL1

t AS t AH

R/W VIL1 VIL1

PW EH t AH
t Ef
VIH1 VIH1
E VIL1 VIL1 VIL1
t Er
t DSW tH
VIH1 VIH1
DB0 to DB7 VIL1 Valid data VIL1
t cycE

Ta=25°C, VDD=5.0± 0.5V

Item Symbol Min Typ Max Unit

Enable cycle time tcycE 400 - - ns

Enable pulse width (high level) PWEH 150 - - ns

Enable rise/fall time tEr,tEf - - 25 ns

Address set-up time (RS, R/W to E) tAS 30 - - ns

Address hold time tAH 10 - - ns

Data set-up time tDSW 40 - - ns

Data hold time tH 10 - - ns

12
 VIH1 VIH1
RS VIL1 VIL1

tAS tAH
VIH1 VIH1
R/W
PW EH t
AH

tEf
VIH1 VIH1
E VIL1 VIL1 VIL1
tEr tDDR tDHR
VOH1 VOH1
DB0 to DB7 VOL1*
Valid data
*VOL1
tcycE

NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation.

11.2 Read Operation

Ta=25°C, VDD=5.0± 0.5V

Item Symbol Min Typ Max Unit

Enable cycle time tcycE 400 - - ns

Enable pulse width (high level) PWEH 150 - - ns

Enable rise/fall time tEr,tEf - - 25 ns

Address set-up time (RS, R/W to E) tAS 30 - - ns

Address hold time tAH 10 - - ns

Data delay time tDDR - - 100 ns

Data hold time tDHR 20 - - ns

13
12. Backlight Information

Specification

PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION

Supply Current ILED ― 280 560 mA V=4.2V

Supply Voltage V - 4.2 4.6 V -

Reverse Voltage VR - - 10 V -
Luminous
IV - 180 - CD/M2 ILED=280mA
Intensity
Wave Length λp ― 570 - nm ILED=280mA

Life Time - - 100000 - Hr. V ≤ 4.6V

14
13. Initializing of LCM

Power on

Wait for more than 15 ms after V CC rises to 4.5 V

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. )
0 0 0 0 1 1 * * * *

Wait for more than 4.1 ms

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. )
0 0 0 0 1 1 * * * *

Wait for more than 100 µs

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. )
0 0 0 0 1 1 * * * *

BF can be checked after the following instructions.

When BF is not checked , the waiting time between
instructions is longer than execution instruction time.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. Specify
0 0 0 0 1 1 N F * * the number of display lines and font. )
0 0 0 0 0 0 1 0 0 0 The number of display lines and character font
0 0 0 0 0 0 0 0 0 1 can not be changed after this point.
0 0 0 0 0 0 0 1 I/D S Display off
Display clear
Entry mode set

Initialization ends

8-Bit Ineterface

15
 Power on

Wait for more than 15 ms after VCC rises to 4.5 V

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4
Function set ( Interface is 8 bits long. )
0 0 0 0 1 1

Wait for more than 4.1 ms

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 Function set ( Interface is 8 bits long. )
0 0 0 0 1 1

Wait for more than 100 µs

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4
Function set ( Interface is 8 bits long. )
0 0 0 0 1 1

RS R/W DB7 DB6 DB5 DB4 BF can be checked after the following instructions.
0 0 0 0 1 0 When BF is not checked , the waiting time between
0 0 0 0 1 0 instructions is longer than execution instruction time.
0 0 N F * *
Function set ( Set interface to be 4 bits long. )
0 0 0 0 0 0 Interface is 8 bits in length.
0 0 1 0 0 0
0 0 0 0 0 0 Function set ( Interface is 4 bits long. Specify
0 0 0 0 0 1 the number of display lines and character font. )
0 0 0 0 0 0 The number of display lines and character font
0 0 0 1 I/D S can not be changed after this point.
Display off
Display clear
Entry mode set

Initialization ends

4-Bit Ineterface

16