FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

August 2000

FM24C08U/09U – 8K-Bit Standard 2-Wire Bus

Interface Serial EEPROM

General Description Features

The FM24C08U/09U devices are 8192 bits of CMOS non-volatile ■ Extended operating voltage 2.7V – 5.5V
electrically erasable memory. These devices conform to all speci- ■ 400 KHz clock frequency (F) at 2.7V - 5.5V
fications in the Standard IIC 2-wire protocol. They are designed to
■ 200µA active current typical
minimize device pin count and simplify PC board layout require-
10µA standby current typical
ments.
1µA standby current typical (L)
The upper half (upper 4Kbit) of the memory of the FM24C09U can 0.1µA standby current typical (LZ)
be write protected by connecting the WP pin to VCC. This section of ■ IIC compatible interface
memory then becomes unalterable unless WP is switched to VSS. – Provides bi-directional data transfer protocol
This communications protocol uses CLOCK (SCL) and DATA ■ Sixteen byte page write mode
I/O (SDA) lines to synchronously clock data between the master – Minimizes total write time per byte
(for example a microprocessor) and the slave EEPROM device(s). ■ Self timed write cycle
The Standard IIC protocol allows for a maximum of 16K of Typical write cycle time of 6ms
EEPROM memory which is supported by the Fairchild family in
■ Hardware Write Protect for upper half (FM24C09U only)
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of ■ Endurance: 1,000,000 data changes
EEPROMs. In order to implement higher EEPROM memory ■ Data retention greater than 40 years
densities on the IIC bus, the Extended IIC protocol must be used.
■ Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
(Refer to the FM24C32 or FM24C65 datasheets for more informa-
tion.) ■ Available in three temperature ranges
- Commercial: 0° to +70°C
Fairchild EEPROMs are designed and tested for applications requir- - Extended (E): -40° to +85C
ing high endurance, high reliability and low power consumption. - Automotive (V): -40° to +125°C

Block Diagram
VCC
VSS
WP
H.V. GENERATION
TIMING &CONTROL

SDA START
STOP
LOGIC

CONTROL
LOGIC
SLAVE ADDRESS
REGISTER & E2PROM
SCL COMPARATOR XDEC ARRAY

A2 WORD
ADDRESS
COUNTER

R/W YDEC

CK
DOUT
DIN DATA REGISTER

© 2000 Fairchild Semiconductor International 1 www.fairchildsemi.com

FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)

NC 1 8 VCC

NC 2 7 NC
24C08
A2 3 6 SCL

VSS 4 5 SDA

See Package Number N08E, M08A and MTC08

Pin Names
A2 Device Address Input
VSS Ground
SDA Serial Data I/O
SCL Serial Clock Input
NC No Connection
VCC Power Supply

Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)

NC 1 8 VCC

NC 2 7 WP
24C09
A2 3 6 SCL

VSS 4 5 SDA

See Package Number N08E, M08A and MTC08

Pin Names
A2 Device Address Input
VSS Ground
SDA Serial Data I/O
SCL Serial Clock input
WP Write Protect
VCC Power Supply
NC No Connection

NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care
should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information
FM 24 C XX U F LZ E XXX Letter Description

Package N 8-pin DIP

M8 8-pin SOIC
MT8 8-pin TSSOP

Temp. Range Blank 0 to 70°C

V -40 to +125°C
E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 5.5V
LZ 2.7V to 5.5V and
<1µA Standby Current

SCL Clock Frequency Blank 100KHz

F 400KHz

Process U Ultralite CS100UL

Density 08 8K
09 8K with Write Protect

C CMOS Technology

Interface 24 IIC

FM Fairchild Non-Volatile
Memory

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications
Absolute Maximum Ratings Operating Conditions
Ambient Storage Temperature –65°C to +150°C Ambient Operating Temperature
FM24C08U/09U 0°C to +70°C
All Input or Output Voltages
FM24C08UE/09UE -40°C to +85°C
with Respect to Ground –0.3V to 6.5V
FM24C08UV/09UV -40°C to +125°C
Lead Temperature
Positive Power Supply
(Soldering, 10 seconds) +300°C
FM24C08U/09U 4.5V to 5.5V
ESD Rating 2000V min. FM24C08UL/09UL 2.7V to 5.5V
FM24C08ULZ/09ULZ 2.7V to 5.5V

DC Electrical Characteristics (2.7V to 5.5V)

Symbol Parameter Test Conditions Limits Units
Min Typ Max
(Note 1)
ICCA Active Power Supply Current fSCL = 400 KHz ("F" version) 0.2 1.0 mA
fSCL = 100 KHz
ISB Standby Current VIN = GND VCC = 2.7V - 5.5V 10 50 µA
(Note 3) or VCC VCC = 2.7V - 5.5V (L) 1 10 µA
VCC = 2.7V - 4.5V (LZ) 0.1 1 µA
ILI Input Leakage Current VIN = GND to VCC 0.1 1 µA
ILO Output Leakage Current VOUT = GND to VCC 0.1 1 µA
VIL Input Low Voltage –0.3 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL Output Low Voltage IOL = 3 mA 0.4 V

Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)

Symbol Test Conditions Max Units
CI/O Input/Output Capacitance (SDA) VI/O = 0V 8 pF
CIN Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF

Note 1: Typical values are TA = 25°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: The "L" and "LZ" versions can be operated in the 2.7V to 5.5V VCC range. However, for a standby current (ISB) of 1µA, the VCC should be within 2.7V to 4.5V.

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
AC Test Conditions AC Testing Input/Output Waveforms
Input Pulse Levels VCC x 0.1 to VCC x 0.9 0.9VCC 0.7VCC
Input Rise and Fall Times 10 ns 0.1VCC 0.3VCC

Input & Output Timing Levels VCC x 0.3 to VCC x 0.7

Output Load 1 TTL Gate and CL = 100 pF

Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol Parameter 100 KHz 400 KHz Units
Min Max Min Max
fSCL SCL Clock Frequency 100 400 KHz
TI Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN 100 50 ns
Pulse width)
tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs
tBUF Time the Bus Must Be Free before 4.7 1.3 µs
a New Transmission Can Start
tHD:STA Start Condition Hold Time 4.0 0.6 µs
tLOW Clock Low Period 4.7 1.5 µs
tHIGH Clock High Period 4.0 0.6 µs
tSU:STA Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
tHD:DAT Data in Hold Time 0 0 ns
tSU:DAT Data in Setup Time 250 100 ns
tR SDA and SCL Rise Time 1 0.3 µs
tF SDA and SCL Fall Time 300 300 ns
tSU:STO Stop Condition Setup Time 4.7 0.6 µs
tDH Data Out Hold Time 300 50 ns
tWR Write Cycle Time
(Note 4) 4.5V to 5.5V VCC 10 10 ms
2.7V to 4.5V VCC 15 15

Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C08U/09U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.

Bus Timing
tF tR

tHIGH

tLOW tLOW

SCL

tSU:STO

;;
tSU:STA tHD:DAT tSU:DAT
tHD:STA
SDA
IN
tBUF

tAA tDH

SDA
OUT

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Cycle Timing

SCL

SDA 8th BIT ACK

WORD n tWR
STOP START
CONDITION CONDITION
Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

Typical System Configuration

VCC VCC

SDA
SCL

Master Slave Master

Slave Master
Transmitter/ Transmitter/ Transmitter/
Receiver Transmitter
Receiver Receiver Receiver

Note: Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)

Example of 16K of Memory on 2-Wire Bus

Note: The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF VCC VCC

SDA
SCL
VCC VCC VCC VCC

24C02/03 24C02/03 24C04/05 24C08/09

A0 A1 A2 VSS A0 A1 A2 VSS A1 A2 VSS A2 VSS

To To To To To To To To To
VSS VSS VSS VCC VSS VSS VCC VSS VCC

Device Address Pins Present Memory Size # of Page

A0 A1 A2 Blocks
FM24C02U/03U Yes Yes Yes 2048 Bits 1
FM24C04U/05U No Yes Yes 4096 Bits 2
FM24C08U/09U No No Yes 8192 Bits 4
FM24C16U/17U No No No 16,384 Bits 8

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Background Information (IIC Bus) Acknowledge
IIC bus allows synchronous bi-directional communication be- Acknowledge is an active LOW pulse on the SDA line driven by an
tween a TRANSMITTER and a RECEIVER using a Clock signal addressed receiver to the addressing transmitter to indicate
(SCL) and a Data signal (SDA). Additionally there are up to three receipt of 8-bits of data. The receiver provides an ACK pulse for
Address signals (A2, A1 and A0) which collectively serve as "chip every 8-bits of data received. This handshake mechanism is done
select signal" to a device (example EEPROM) on the IIC bus. as follows: After transmitting 8-bits of data, the transmitter re-
leases the SDA line and waits for the ACK pulse. The addressed
All communication on the IIC bus must be started with a valid receiver, if present, drives the ACK pulse on the SDA line during
START condition (by a MASTER), followed by transmittal (by the the 9th clock and releases the SDA line back (to the transmitter).
MASTER) of byte(s) of information (Address/Data). For every byte Refer Figure 3.
of information received, the addressed RECEIVER provides a valid
ACKNOWLEDGE pulse to further continue the communication Array Address
unless the RECEIVER intends to discontinue the communication.
Array address is an 8-bit information containing the address of a
Depending on the direction of transfer (Write or Read), the RE-
memory location to be selected within a page block of the device.
CEIVER can be a SLAVE or the MASTER. A typical IIC communi-
cation concludes with a STOP condition (by the MASTER). 16K bit Addressing Limitation:
Addressing an EEPROM memory location involves sending a Standard IIC specification limits the maximum size of EEPROM
command string with the following information: memory on the bus to 16K bits. This limitation is due to the
addressing protocol implemented which consists of the 8-bit Slave
[DEVICE TYPE]—[DEVICE/PAGE BLOCK SELECTION]—[R/W
Address and an additional 8-bit field called Array Address. This
BIT]—{acknowledge pulse}—[ARRAY ADDRESS]
Array Address selects 1 out of 256 locations (28=256). Since the
data format of IIC specification is 8-bit wide, a total of 256 x 8 =
Slave Address 2048 = 2K bits now becomes addressable by this 8-bit Array
Slave Address is an 8-bit information consisting of a Device type Address. These 2K bits are typically referred as a “Page Block”.
field (4bits), Device/Page block selection field (3bits) and Read/ Combining this 8-bit Array Address with the 3-bit Device/Page
Write bit (1bit). address (part of Slave Address) allows a maximum of 8 pages
(23=8) of memory that can be addressed. Since each page is 2K
Slave Address Format bits in size, 8 x 2K bit = 16K bits is the maximum size of memory
Device Type Device/Page Block that is addressable on the Standard IIC bus. This 16Kb of memory
Identifier Selection can be in the form of a single 16Kb EEPROM device or multiple
EEPROMs of varying density (in 2Kb multiples) to a maximum
total of 16Kb. To address the needs of systems that require more
1 0 1 0 A2 A1 A0 R/W (LSB) than 16Kb on the IIC bus, a different specification called “Ex-
tended IIC Specification” is used.

Device Type DEFINITIONS

IIC bus is designed to support a variety of devices such as RAMs, WORD 8 bits (byte) of data
EPROMs etc., along with EEPROMS. Hence to properly identify
various devices on the IIC bus, a 4-bit “Device Type” identifier PAGE 16 sequential byte locations
string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC starting at a 16-byte address
device on the bus internally compares this 4-bit string to its own boundary, that may be pro-
“Device Type” string to ensure proper device selection. grammed during a "page write"
programming cycle
Device/Page Block Selection
PAGE BLOCK 2048 (2K) bits organized into 16
When multiple devices of the same type (e.g. multiple EEPROMS) pages of addressable memory. (8
are present on the IIC bus, then the A2, A1 and A0 address bits) x (16 bytes) x (16 pages) =
information bits are also used as part of the Slave Address. Every 2048 bits
IIC device on the bus internally compares this 3-bit string to its own
MASTER Any IIC device CONTROLLING the
physical configuration (A2, A1 and A0 pins) to ensure proper
transfer of data (such as a
device selection. This comparison is in addition to the “Device
microprocessor)
Type” comparison. In addition to selecting an EEPROM, these 3
bits are also used to select a “page block” within the selected SLAVE Device being controlled
EEPROM. Each page block is 2Kbit (256Bytes) in size. Depend- (EEPROMs are always considered
ing on the density, an EEPROM can contain from a minimum of 1 Slaves)
to a maximum of 8 page blocks (in multiples of 2) and selection of
a page block within a device is by using A2, A1 and A0 bits. TRANSMITTER Device currently SENDING data on
the bus (may be either a Master or
Read/Write Bit Slave).
Last bit of the Slave Address indicates if the intended access is RECEIVER Device currently RECEIVING data
Read or Write. If the bit is "1," then the access is Read, whereas on the bus (Master or Slave)
if the bit is "0," then the access is Write.

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Pin Descriptions Device Operation
Serial Clock (SCL) The FM24C08U/09U supports a bi-directional bus oriented proto-
col. The protocol defines any device that sends data onto the bus
The SCL input is used to clock all data into and out of the device. as a transmitter and the receiving device as the receiver. The
Serial Data (SDA) device controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
SDA is a bi-directional pin used to transfer data into and out of the transfers and provide the clock for both transmit and receive
device. It is an open drain output and may be wire–ORed with any operations. Therefore, the FM24C08U/09U will be considered a
number of open drain or open collector outputs. slave in all applications.
Write Protect (WP) (FM24C09U Only) Clock and Data Conventions
If tied to VCC, PROGRAM operations onto the upper half (upper Data states on the SDA line can change only during SCL LOW.
4Kbits) of the memory will not be executed. READ operations are SDA state changes during SCL HIGH are reserved for indicating
possible. If tied to VSS, normal operation is enabled, READ/ start and stop conditions. Refer to Figure 1 and Figure 2 on next
WRITE over the entire memory is possible. page.
This feature allows the user to assign the upper half of the memory Start Condition
as ROM which can be protected against accidental programming. All commands are preceded by the start condition, which is a
When write is disabled, slave address and word address will be HIGH to LOW transition of SDA when SCL is HIGH. The
acknowledged but data will not be acknowledged. FM24C08U/09U continuously monitors the SDA and SCL lines for
This pin has an internal pull-down circuit. However, on systems the start condition and will not respond to any command until this
where write protection is not required it is recommended that this condition has been met.
pin is tied to VSS.
Stop Condition
Device Selection Inputs A2, A1 and A0 (as All communications are terminated by a stop condition, which is a
appropriate) LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C08U/09U to place the device
These inputs collectively serve as “chip select” signal to an
in the standby power mode, except when a Write operation is
EEPROM when multiple EEPROMs are present on the same IIC
being executed, in which case a second stop condition is required
bus. Hence these inputs, if present, should be connected to VCC
after tWR period, to place the device in standby mode.
or VSS in a unique manner to allow proper selection of an EEPROM
amongst multiple EEPROMs. During a typical addressing se-
quence, every EEPROM on the IIC bus compares the configura-
tion of these inputs to the respective 3 bit “Device/Page block
selection” information (part of slave address) to determine a valid
selection. For e.g. if the 3 bit “Device/Page block selection” is 1-
0-1, then the EEPROM whose “Device Selection inputs” (A2, A1
and A0) are connected to VCC-VSS-VCC respectively, is selected.
Depending on the density, only appropriate number of “Device
Selection inputs” are provided on an EEPROM. For every “Device
selection input” that is not present on the device, the correspond-
ing bit in the “Device/Page block selection” field is used to select
a “Page Block” within the device instead of the device itself.
Following table illustrates the above:

EEPROM Number of Device Selection Inputs Address Bits

Density Page Blocks Provided Selecting Page Block
2k bit 1 A0 A1 A2 None
4k bit 2 — A1 A2 A0
8k bit 4 — — A2 A0 and A1
16k bit 8 — — — A0, A1 and A2

Note that even when just one EEPROM present on the IIC bus,
these pins should be tied to VCC or VSS to ensure proper termina-
tion.

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Data Validity (Figure 1)

SCL

SDA
DATA STABLE DATA
CHANGE

Start and Stop Definition (Figure 2)

SCL

SDA

START STOP
CONDITION CONDITION

Acknowledge Response from Receiver (Figure 3)

SCL FROM
MASTER 1 8 9

DATA OUTPUT
FROM
TRANSMITTER
tDH
tAA
DATA OUTPUT
FROM
RECEIVER

START ACKNOWLEDGE
CONDITION PULSE

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Acknowledge Refer the following table for Slave Addresses string details:

The FM24C08U/09U device will always respond with an acknowl- Device A0 A1 A2 Page Page Block
edge after recognition of a start condition and its slave address. If
Blocks Addresses
both the device and a write operation have been selected, the
FM24C08U/09U will respond with an acknowledge after the FM24C08U/09U P P A 4 00, 01, 10, 11
receipt of each subsequent eight bit byte.
A: Refers to a hardware configured Device Address pin.
In the read mode the FM24C08U/09U slave will transmit eight bits P: Refers to an internal PAGE BLOCK.
of data, release the SDA line and monitor the line for an acknowl- All IIC EEPROMs use an internal protocol that defines a PAGE
edge. If an acknowledge is detected, FM24C08U/09U will continue BLOCK size of 2K bits (for Word addresses 0x00 through 0xFF).
to transmit data. If an acknowledge is not detected,FM24C08U/09U Therefore, address bits A0, A1, or A2 (if designated 'P') are used
will terminate further data transmissions and await the stop condi- to access a PAGE BLOCK in conjunction with the Word address
tion to return to the standby power mode. used to access any individual data byte.
Device Addressing The last bit of the slave address defines whether a write or read
Following a start condition the master must output the address of condition is requested by the master. A '1' indicates that a read
the slave it is accessing. The most significant four bits of the slave operation is to be executed, and a '0' initiates the write mode.
address are those of the device type identifier. This is fixed as A simple review: After the FM24C08U/09U recognizes the start
1010 for all EEPROM devices. condition, the devices interfaced to the IIC bus wait for a slave
Device Type Device address to be transmitted over the SDA line. If the transmitted
Identifier Address slave address matches an address of one of the devices, the
designated slave pulls the SDA line LOW with an acknowledge
signal and awaits further transmissions.
1 0 1 0 A2 A1 A0 R/W (LSB)

24C08/09
Page
Block Address

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Operations
BYTE WRITE Page Write is initiated in the same manner as the Byte Write
operation; but instead of terminating the cycle after transmitting
For a write operation, a second address field is required which is a the first data byte, the master can further transmit up to 15 more
word address that is comprised of eight bits and provides access to bytes. After the receipt of each byte, FM24C08U/09U will respond
any one of the 256 bytes in the selected page of memory. Upon with an acknowledge pulse, increment the internal address counter
receipt of the byte address, the FM24C08U/09U responds with an to the next address, and is ready to accept the next data. If the
acknowledge and waits for the next eight bits of data, again, master should transmit more than sixteen bytes prior to generat-
responding with an acknowledge. The master then terminates the ing the STOP condition, the address counter will “roll over” and
transfer by generating a stop condition at which time the FM24C08U/ previously written data will be overwritten. As with the Byte Write
09U begins the internal write cycle to the nonvolatile memory. While operation, all inputs are disabled until completion of the internal
the internal write cycle is in progress, the FM24C08U/09U inputs write cycle. Refer to Figure 5 for the address, acknowledge, and
are disabled, and the device will not respond to any requests from data transfer sequence.
the master for the duration of tWR. Refer to Figure 4 for the address,
acknowledge, and data transfer sequence. Acknowledge Polling
PAGE WRITE Once the stop condition is issued to indicate the end of the host’s
write operation, the FM24C08U/09U initiates the internal write
To minimize write cycle time, FM24C08U/09U offer Page Write cycle. ACK polling can be initiated immediately. This involves
feature, by which, up to a maximum of 16 contiguous byte issuing the start condition followed by the slave address for a write
locations can be programmed all at once (instead of 16 individual operation. If the FM24C08U/09U is still busy with the write
byte writes). To facilitate this feature, the memory array is orga- operation, no ACK will be returned. If the FM24C08U/09U has
nized in terms of “Pages.” A Page consists of 16 contiguous byte completed the write operation, an ACK will be returned and the
locations starting at every 16-Byte address boundary (for ex- host can then proceed with the next read or write operation.
ample, starting at array address 0x00, 0x10, 0x20 etc.). Page
Write operation limits access to byte locations within a page. In Write Protection (FM24C09U Only)
other words a single Page Write operation will not cross over to Programming of the upper half (upper 4Kbit) of the memory will not
locations on another page but will “roll over” to the beginning of the take place if the WP pin of the FM24C09U is connected to VCC.
page whenever end of Page is reached and additional locations The FM24C09U will respond to slave and byte addresses; but if
are continued to be accessed. A Page Write operation can be the memory accessed is write protected by the WP pin, the
initiated to begin at any location within a page (starting address of FM24C09U will not generate an acknowledge after the first byte
the Page Write operation need not be the starting address of a of data has been received. Thus the program cycle will not be
Page). started when the stop condition is asserted.

Byte Write (Figure 4)

S
T S
Bus Activity: A SLAVE WORD T
Master R ADDRESS ADDRESS DATA O
T P

SDA Line
A A A
Bus Activity: C C C
EEPROM K K K

Page Write (Figure 5)

S
T S
Bus Activity: A SLAVE T
ADDRESS WORD ADDRESS (n) DATA n DATA n + 1 DATA n + 15 O
Master R
T P

SDA Line
A A A A A
Bus Activity: C C C C C
EEPROM K K K K K

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FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Read Operations immediately issues another start condition and the slave address
with the R/W bit set to one. This will be followed by an acknowl-
Read operations are initiated in the same manner as write edge from the FM24C08U/09U and then by the eight bit word. The
operations, with the exception that the R/W bit of the slave master will not acknowledge the transfer but does generate the
address is set to a one. There are three basic read operations: stop condition, and therefore the FM24C08U/09U discontinues
current address read, random read, and sequential read. transmission. Refer to Figure 7 for the address, acknowledge, and
data transfer sequence.
Current Address Read
Internally the FM24C08U/09U contains an address counter that Sequential Read
maintains the address of the last byte accessed, incremented by Sequential reads can be initiated as either a current address read
one. Therefore, if the last access (either a read or write) was to or random access read. The first word is transmitted in the same
address n, the next read operation would access data from manner as the other read modes; however, the master now
address n + 1. Upon receipt of the slave address with R/W set to responds with an acknowledge, indicating it requires additional
one, the FM24C08U/09U issues an acknowledge and transmits data. The FM24C08U/09U continues to output data for each
the eight bit word. The master will not acknowledge the transfer acknowledge received. The read operation is terminated by the
but does generate a stop condition, and therefore the FM24C08U/ master not responding with an acknowledge or by generating a
09U discontinues transmission. Refer to Figure 6 for the se- stop condition.
quence of address, acknowledge and data transfer.
The data output is sequential with the data from address n
Random Read followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
Random read operations allow the master to access any memory
memory contents to be serially read during one operation. After
location in a random manner. Prior to issuing the slave address
the entire memory has been read, the counter "rolls over" to the
with the R/W bit set to one, the master must first perform a
beginning of the memory. FM24C08U/09U continues to output
“dummy” write operation. The master issues the start condition,
data for each acknowledge received. Refer to Figure 8 for the
slave address with the R/W bit set to zero and then the byte
address, acknowledge, and data transfer sequence.
address is read. After the byte address acknowledge, the master

Current Address Read (Figure 6)

S
T S
Bus Activity: A SLAVE T
Master R ADDRESS O
T P

SDA Line 1 0 1 0 1
A NO
Bus Activity: C A
EEPROM DATA
K C
K

Random Read (Figure 7)

S S
T T S
A SLAVE WORD A SLAVE T
Bus Activity:
R ADDRESS ADDRESS R ADDRESS O
Master
T T P

SDA Line
A A A NO
Bus Activity: C C C DATA n A
EEPROM K K K C
K

Sequential Read (Figure 8)

S
Bus Activity: A A A T
Master Slave C C C O
Address P
K K K

SDA Line
A NO
C DATA n +1 DATA n +1 DATA n + 2 DATA n + x A
Bus Activity:
EEPROM K C
K

12 www.fairchildsemi.com
FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)

8 7 6 5

0.228 - 0.244
(5.791 - 6.198)

1 2 3 4
Lead #1
IDENT

0.150 - 0.157
(3.810 - 3.988) 0.053 - 0.069
0.010 - 0.020 (1.346 - 1.753) 0.004 - 0.010
x 45¡ 8¡ Max, Typ.
(0.254 - 0.508) (0.102 - 0.254)
All leads
Seating
0.004 Plane
0.0075 - 0.0098 (0.102) 0.014
(0.190 - 0.249) All lead tips 0.016 - 0.050 (0.356)
Typ. All Leads (0.406 - 1.270) 0.050 0.014 - 0.020 Typ.
Typ. All Leads (1.270) (0.356 - 0.508)
Typ

8-Pin Molded Small Outline Package (M8)

Package Number M08A

0.114 - 0.122
(2.90 - 3.10)

8 5

(4.16) Typ (7.72) Typ

0.169 - 0.177
0.246 - 0.256
(4.30 - 4.50)
(6.25 - 6.5)
(1.78) Typ

0.123 - 0.128 (0.42) Typ

(3.13 - 3.30) (0.65) Typ

1 4 Land pattern recommendation

Pin #1 IDENT

0.0433
Max
(1.1)

See detail A 0.0035 - 0.0079

0.002 - 0.006
(0.05 - 0.15)

0.0256 (0.65)
Typ. Gage
0.0075 - 0.0118
(0.19 - 0.30) plane
0¡-8¡

DETAIL A
Typ. Scale: 40X 0.0075 - 0.0098
0.020 - 0.028 Seating (0.19 - 0.25)
(0.50 - 0.70) plane

Notes: Unless otherwise specified

1. Reference JEDEC registration MO153. Variation AA. Dated 7/93

8-Pin Molded Thin Shrink Small Outline Package (MT8)

Package Number MTC08

13 www.fairchildsemi.com
FM24C08U/09U Rev. A.3
 FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)

0.090
(2.286) 0.032 ± 0.005 8 7
8 7 6 5 (0.813 ± 0.127)
0.092 RAD
DIA
(2.337)
0.250 - 0.005 Pin #1
Pin #1 IDENT + IDENT
(6.35 ± 0.127)
Option 1 1
1 2 3 4
0.280 MIN Option 2
0.040 Typ.
(7.112)
0.030 (1.016) 0.039 0.145 - 0.200
MAX
0.300 - 0.320 (0.762)
20° ± 1° (0.991) (3.683 - 5.080)
(7.62 - 8.128)

0.130 ± 0.005
(3.302 ± 0.127)

0.125 - 0.140
95° ± 5°
0.065 (3.175 - 3.556)
0.125 0.020
0.009 - 0.015 (1.651) 90° ± 4°
(3.175) Typ (0.508)
(0.229 - 0.381) DIA
NOM 0.018 ± 0.003 Min
+0.040
0.325 -0.015 (0.457 ± 0.076)
+1.016 0.100 ± 0.010
8.255 -0.381
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381) 0.060
(1.524)
0.050
(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, 2. A critical component is any component of a life support device
(a) are intended for surgical implant into the body, or (b) support or system whose failure to perform can be reasonably ex-
or sustain life, and whose failure to perform, when properly pected to cause the failure of the life support device or system,
used in accordance with instructions for use provided in the or to affect its safety or effectiveness.
labeling, can be reasonably expected to result in a significant
injury to the user.

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Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FM24C08U/09U Rev. A.3
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