STD45NF75

N-CHANNEL 75V - 0.018 Ω -40A DPAK

STripFET™ II POWER MOSFET

TYPE VDSS RDS(on) ID

STD45NF75 75 V <0.024 Ω 40 A(**)

■ TYPICAL RDS(on) = 0.018 Ω
■ 100% AVALANCHE TESTED
■ GATE CHARGE MINIMIZED
■ SURFACE-MOUNTING DPAK (TO-252) 3
POWER PACKAGE IN TAPE & REEL 1
(SUFFIX “T4") DPAK
TO-252
DESCRIPTION (Suffix “T4”)
This Power MOSFET is the latest development of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalanche characteristics and
less critical alignment steps therefore a INTERNAL SCHEMATIC DIAGRAM
remarkable manufacturing reproducibility.

APPLICATIONS
■ HIGH CURRENT, SWITCHING

APPLICATIONS

Ordering Information
SALES TYPE MARKING PACKAGE PACKAGING
STD45NF75T4 D45NF75 DPAK TAPE & REEL

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 75 V
VDGR Drain-gate Voltage (RGS = 20 kΩ) 75 V
VGS Gate- source Voltage ± 20 V
ID(**) Drain Current (continuous) at TC = 25°C 40 A
ID Drain Current (continuous) at TC = 100°C 30 A
IDM(•) Drain Current (pulsed) 160 A
Ptot Total Dissipation at TC = 25°C 100 W
Derating Factor 0.67 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 20 V/ns
EAS (2) Single Pulse Avalanche Energy 500 mJ
Tstg Storage Temperature
-55 to 175 °C
Tj Operating Junction Temperature
(•) Pulse width limited by safe operating area. (1) ISD ≤40A, di/dt ≤800A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
(**) Current Limited by Package (2) Starting Tj = 25 oC, ID = 20 A, VDD = 40V
April 2004 1/12
STD45NF75

THERMAL DATA
Rthj-case Thermal Resistance Junction-case Max 1.5 °C/W
Rthj-pcb Thermal Resistance Junction-pcb Max see curve on page 6 °C/W

Tl Maximum Lead Temperature For Soldering Purpose 275 °C

(for 10 sec. 1.6 mm from case)

ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified)

OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source ID = 250 µA VGS = 0 75 V

Breakdown Voltage

IDSS Zero Gate Voltage VDS = Max Rating 1 µA

Drain Current (VGS = 0) VDS = Max Rating TC = 125°C 10 µA

Gate-body Leakage VGS = ± 20 V ±100 nA

IGSS
Current (VDS = 0)

ON (*)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA 2 4 V

RDS(on) Static Drain-source On VGS = 10 V ID = 20 A 0.018 0.024 Ω

Resistance

DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit

gfs (*) Forward Transconductance VDS = 25 V ID = 20 A 50 S

Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 1760 pF

Coss Output Capacitance 360 pF
Crss Reverse Transfer 140 pF
Capacitance

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 STD45NF75

ELECTRICAL CHARACTERISTICS (continued)

SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit

td(on) Turn-on Delay Time VDD = 37 V ID = 20 A 15 ns

tr Rise Time RG = 4.7 Ω VGS = 10 V 40 ns
(Resistive Load, Figure 3)
Qg Total Gate Charge VDD=60 V ID=40A VGS= 10V 60 80 nC
Qgs Gate-Source Charge 13 nC
Qgd Gate-Drain Charge (see test circuit, Figure 4) 23 nC

SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit

td(off) Turn-off Delay Time VDD = 37 V ID = 20 A 55 ns

tf Fall Time RG = 4.7Ω, VGS = 10 V 12 ns
(Resistive Load, Figure 3)

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 40 A
ISDM (•) Source-drain Current (pulsed) 160 A

VSD (*) Forward On Voltage ISD = 40 A VGS = 0 1.5 V

trr Reverse Recovery Time ISD = 40 A di/dt = 100A/µs 120 ns

Qrr Reverse Recovery Charge VDD = 30 V Tj = 150°C 410 nC
IRRM Reverse Recovery Current (see test circuit, Figure 5) 7.5 A
(*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.

Safe Operating Area Thermal Impedance

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STD45NF75

Output Characteristics Transfer Characteristics

Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations

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 STD45NF75

Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature

Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature.

.
Power Derating vs Tc .
Max Id Current vs Tc.

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STD45NF75

Thermal Resistance Rthj-a vs PCB Copper Area Max Power Dissipation vs PCB Copper Area

Allowable Iav vs. Time in Avalanche

The previous curve gives the safe operating area for unclamped inductive loads, single pulse or repetitive,
under the following conditions:

PD(AVE) = 0.5 * (1.3 * BVDSS * IAV)

EAS(AR) = PD(AVE) * tAV

Where:
IAV is the Allowable Current in Avalanche
PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse)
tAV is the Time in Avalanche

To derate above 25 oC, at fixed IAV, the following equation must be applied:

IAV = 2 * (Tjmax - TCASE)/ (1.3 * BVDSS * Zth)

Where:
Zth = K * Rth is the value coming from Normalized Thermal Response at fixed pulse width equal to TAV .

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 STD45NF75

SPICE THERMAL MODEL

Parameter Node Value

CTHERM1 7-6 6 * 10-4

CTHERM2 6-5 8 * 10-3
CTHERM3 5-4 2 * 10-2
CTHERM4 4-3 6 * 10-2
CTHERM5 3-2 9.65 * 10-2
CTHERM6 2-1 6 * 10-1

RTHERM1 7-6 0.045

RTHERM2 6-5 0.105
RTHERM3 5-4 0.150
RTHERM4 4-3 0.225
RTHERM5 3-2 0.375
RTHERM6 2-1 0.600

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STD45NF75

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuits For Resistive Fig. 3.1: Switching Time Waveform
Load

Fig. 4: Gate Charge Test Circuit Fig. 4.1: Gate Charge Test Waveform

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 STD45NF75

Fig. 5: Diode Switching Test Circuit Fig. 5.1: Diode Recovery Times Waveform

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STD45NF75

TO-252 (DPAK) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.2 2.4 0.086 0.094

A1 0.9 1.1 0.035 0.043

A2 0.03 0.23 0.001 0.009

B 0.64 0.9 0.025 0.035

B2 5.2 5.4 0.204 0.212

C 0.45 0.6 0.017 0.023

C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244

E 6.4 6.6 0.252 0.260

G 4.4 4.6 0.173 0.181

H 9.35 10.1 0.368 0.397

L2 0.8 0.031

L4 0.6 1 0.023 0.039

H
A

C2

A1

DETAIL "A"
C

A2

L2 D
DETAIL "A"
B
3
=

=
B2

G
E

2
=

=
1

L4
0068772-B

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STD45NF75

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STD45NF75

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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© 2004 STMicroelectronics - All Rights Reserved

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