Skip to content
View ArturBieniek4's full-sized avatar
17 followers · 19 following

Highlights

  • Pro

Organizations

@verilator @kuznia-rdzeni

Block or report ArturBieniek4

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
ArturBieniek4/README.md

Artur Bieniek

I work on Verilator at Antmicro,
focusing on SystemVerilog support, simulation correctness and performance.

Website LinkedIn My Verilator pull requests

C++ C SystemVerilog Linux

Selected open-source work

SystemVerilog assertions

Temporal logic & simulation performance

Developing NFA-based SystemVerilog assertion support in Verilator. Optimized large repetitions by replacing expanded state chains with compact ring buffers.

Ring-buffer optimization ↗

Force / release

Language semantics & simulation correctness

Rebuilt Verilator's force/release handling around runtime tracking, fixing the semantics of conditional and overlapping forces.

Implementation ↗ · B.Eng. thesis ↗

Background & interests

I'm an M.Sc. student in Computer Science at the University of Wrocław. Beyond hardware simulation, I'm interested in security research, reverse engineering and hardware.

CTFs: Break The Syntax 2026 - 2nd place (as a team)

GitHub activity

GitHub statistics

Profile views

Pinned Loading

  1. verilator/verilator verilator/verilator Public

    Verilator open-source SystemVerilog simulator and lint system

    SystemVerilog 4k 916

  2. BTS2026-CTF-Writeups BTS2026-CTF-Writeups Public

    Writeups (not official) by me & my team for Break The Syntax 2026 CTF

    PHP

  3. engineering-thesis engineering-thesis Public archive

    My engineering thesis about implementing force/release in Verilator

    TeX

  4. sha3x_cudaminer sha3x_cudaminer Public archive

    A fast SHA3X CUDA miner

    Rust

  5. University University Public

    C 3

  6. kuznia-rdzeni/coreblocks kuznia-rdzeni/coreblocks Public

    RISC-V out-of-order core for education and research purposes

    Python 99 27