upf

Here are 4 public repositories matching this topic...

ed766 / ucie_chiplet_soc

Firmware-driven dual-die RV32 chiplet SoC with GCC/ISS co-verification, DMA/AES offload, UPF 4.0 low-power intent, async CDC, real UVM, formal, and open-source coverage.

riscv systemverilog cdc formal-verification low-power verilator upf design-verification ucie librelane

Updated Aug 13, 2026
SystemVerilog

A modular, open-source Power Management Unit (PMU) integrated into the PULP Croc SoC — an open-source RISC-V SoC based on the CVE2 (Ibex) core. Implements clock gating and power gating via UPF (IEEE 1801), using a fully open-source RTL-to-GDSII flow.

systemverilog risc-v power-management open-source-hardware upf power-gating pulp-platform clock-gating croc-soc

Updated May 7, 2026
SystemVerilog

ErickOF / LPCGRAMeth

Star

Low-Power CGRA Design Methodology (WIP)

verilog vcs systemverilog synopsys hdl uvm hardware-acceleration parallel-processing low-power verdi cgra upf dvt uvm-verification uvm-testbench

Updated Apr 15, 2026
SystemVerilog

Olajide-Badejo / Low-Power-Async-CDC-FIFO-IP

Star

Parameterized asynchronous CDC FIFO IP: gray-code pointers, a sweepable N-flop synchronizer, IEEE 1801 UPF low-power intent, SymbiYosys formal proofs, and a 60-config Yosys/OpenSTA PPA sweep on SkyWater Sky130. Fully open-source and reproducible.

asic rtl systemverilog fifo cdc formal-verification yosys digital-design low-power upf clock-domain-crossing static-timing-analysis opensta symbiyosys open-source-eda sky130

Updated Jul 16, 2026
SystemVerilog

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upf

Here are 4 public repositories matching this topic...

ed766 / ucie_chiplet_soc

joboscanprojects / croc-pmu

ErickOF / LPCGRAMeth

Olajide-Badejo / Low-Power-Async-CDC-FIFO-IP

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