Six-stage pipelined Bfloat16 FMA in SystemVerilog with simulation, targeted formal verification, FPGA testing, and a SKY130 Tiny Tapeout submission.
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Sep 2, 2026 - SystemVerilog
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bfloat16
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Formal (VC Formal FPV) and UVM verification of an 8-lane mixed-precision INT8/BF16/NVFP4 dot-product core, with a shared SystemVerilog golden reference across assertions and scoreboards.
eda rtl systemverilog uvm formal-verification int8 sva dot-product questa hardware-verification mixed-precision design-verification bfloat16 nvfp4 vc-formal assume-guarantee
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Sep 24, 2026 - SystemVerilog
Parametric structural adders and multipliers in SystemVerilog: unsigned, signed (Baugh-Wooley and radix-4 Booth) and floating point (FP8 e4m3/e5m2, bf16, fp16), verified exhaustively and placed and routed on sky130 (41-design area-delay sweep)
asic rtl systemverilog floating-point adder iverilog multiplier verilator brent-kung computer-arithmetic bfloat16 booth-multiplier openlane sky130 kogge-stone baugh-wooley dadda-multiplier fp8 wallace-tree signed-multiplier
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Sep 20, 2026 - SystemVerilog
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