FreeRTOS porting on 8-stage pipelined RISC-V CPU with HDMI and keyboards

try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor

Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.

fast rv64im emulator for web

Assembly target types and data structures