Code release for "LLMs can see and hear without any training"

Kolmogorov Arnold Networks

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Rocket Chip Generator

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

A full Python implementation for real car surround view system

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

使用Python编写的围棋游戏

When I implemented a peripherial hardware library, which has some interface module like UART, SPI, I2C,GPIO, TIMER, DMA and SoC bus system, I have read a book "DIY CPU" by Lei Silei, and I decided …

This project realized a verified generic implementation of a modular peripheral hardware library with the use of a generic Wishbone Bus system. A Wishbone bus system based on a shared bus architect…