XiangShan
Open-source high-performance RISC-V processor
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Showing 10 of 101 repositories
- XiangShanLab Public
A learning and practice repository for the open-source XiangShan RISC-V processor, featuring a full pathway from environment setup to microarchitecture optimization, designed for developers, students, and researchers.
- GEM5 Public
- XSCache Public
Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.
- XSAICache Public Forked from OpenXiangShan/XSCache
A fork of XSCache for XSAI. Supports High-Bandwidth L2 Cache design.
- ready-to-run Public
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