Skip to content
View Algo-Goer's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report Algo-Goer

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

Showing results

利润是市场给的,都是概率的事儿,谁也别吹牛逼

Python 265 120 Updated Jun 20, 2026

面向开发者的 LLM 入门教程,吴恩达大模型系列课程中文版

Jupyter Notebook 1 Updated Jun 3, 2025

A software framework for building AI agents through composition.

Python 28 8 Updated Sep 22, 2025

👩🏿‍💻👨🏾‍💻👩🏼‍💻👨🏽‍💻👩🏻‍💻中国独立开发者项目列表 -- 分享大家都在做什么

48,941 4,199 Updated Jun 23, 2026

No fortress, purely open ground. OpenManus is Coming.

Python 56,625 9,847 Updated Feb 11, 2026

🙌 OpenHands: AI-Driven Development

Python 78,064 9,923 Updated Jun 23, 2026

Ultra-high-performance, secure, all-in-one acceleration engine for developer resources

JavaScript 8,146 1,277 Updated Jun 22, 2026

Puzzles for learning Triton

Jupyter Notebook 2,499 240 Updated Apr 1, 2026

Repo for counting stars and contributing. Press F to pay respect to glorious developers.

276,312 20,819 Updated Aug 22, 2025

可能是最简单的京东抢购脚本了,以抢茅台为例

JavaScript 124 34 Updated Feb 5, 2021

CEACStatTracker

Python 41 14 Updated Apr 8, 2024

欧港新CS留学项目指北

HTML 783 60 Updated Aug 25, 2025

some resources and records about IELTS for rabbit and penguin

26 10 Updated Apr 25, 2022

IOPMP IP

SystemVerilog 25 7 Updated Jul 11, 2025

RISC-V IOMMU Specification

C 164 33 Updated Jun 8, 2026

DDR2 memory controller written in Verilog

Verilog 83 33 Updated Feb 28, 2012

《从头写一个RISC-V OS》课程配套的资源

C 1,123 268 Updated May 10, 2026

HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI

C 37 14 Updated Dec 24, 2024

平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本

LLVM 76 17 Updated Mar 15, 2021

SystemVerilog Functional Coverage for RISC-V ISA

SystemVerilog 36 13 Updated Dec 11, 2025
C 5 3 Updated Aug 19, 2022

Instruction Set Generator initially contributed by Futurewei

C++ 309 78 Updated Oct 17, 2023

简单的RISC-V指令模拟器,实现了绝大多非扩展指令的模拟工作。

C++ 24 6 Updated Aug 11, 2017

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Assembly 2,976 964 Updated Jun 22, 2026

体系结构研讨 + ysyx高阶大纲 (WIP

217 19 Updated Oct 14, 2024

The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.

Verilog 58 26 Updated Nov 29, 2018

Clash for Windows使用教程,Clash-for-Windows配置,Clash-for-Windows说明,Clash-for-Windows

939 80 Updated Dec 16, 2025

翻墙、免费翻墙、免费科学上网、免费节点、免费梯子、免费ss/ssr/v2ray/trojan节点、蓝灯、谷歌商店、翻墙梯子 、外网游戏、国外游戏、vpn、vpn推荐、每天更新、上外网、外网、V2rayN、Qv2ray、V2rayW、V2RayS、Mellow、V2rayX、V2rayU、ClashX、Kitsunebi、BifrostV、i2Ray 、Quantumult、Surge 4、w…

6,534 480 Updated Jun 6, 2026

Notes taken by zweix while learning computer related knowledge

131 6 Updated Jun 9, 2026

rust-rustlings-2023-autumn-Algo-Goer created by GitHub Classroom

Rust 1 Updated Oct 22, 2023
Next