Skip to content
View Archit-turing's full-sized avatar

Block or report Archit-turing

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. ext_ibex_processor ext_ibex_processor Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog

  2. ext_syntacore_riscv ext_syntacore_riscv Public

    Forked from syntacore/scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog

  3. ext_zipcpu ext_zipcpu Public

    Forked from ZipCPU/zipcpu

    A small, light weight, RISC CPU soft core

    Verilog

  4. ext_VerilogBoy ext_VerilogBoy Public

    Forked from zephray/VerilogBoy

    A Pi emulating a GameBoy sounds cheap. What about an FPGA?

    Verilog