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3D printed DSLR tracking mount
the Network Protocol Fuzzer that we will want to use.
A compact portable X25519 + Ed25519 implementation
ed25519 public key signature implemented in Verilog.
A curated list of fuzzing resources ( Books, courses - free and paid, videos, tools, tutorials and vulnerable applications to practice on ) for learning Fuzzing and initial phases of Exploit Develo…
CLI tool and library for generating a Software Bill of Materials from container images and filesystems
A tool for modifying and replaying 5G protocol network traffic using attack injection and fuzzing.
A curated list of awesome Fuzzing(or Fuzz Testing) for software security
Code security scanning tool (SAST) to discover, filter and prioritize security and privacy risks.
RAN simulator with E2 termination compliant with flexric supports E2AP v1.01, KPM v3 and pre-RC v1.01
An automation tool for deploying 5G Open RAN (O-RAN) testbeds.
SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitatio…
Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
Hardware implementation of the SipHash short-inout PRF
Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
Small footprint and configurable Ethernet core
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
The original sources of MS-DOS 1.25, 2.0, and 4.0 for reference purposes
Framework to control Oscilloscopes, SMUs, Function Generators and DC Powersupplies via Ethernet.
In this paper, a series of Ring Oscillators has been wired in different ways to form Ring Oscillator PUFs to find out the RO PUF which has a better quality. Thus, three different routing methods ar…
Overleaf docker image with all packages available to tlmgr
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 1…
Deadline countdowns for academic conferences in Security and Privacy
Framework to control Oscilloscopes, SMUs, Function Generators and DC Powersupplies via Ethernet.
Open source implementation of the RaSTA protocol (Railsafe Transport Application)