Stars
An open source toolkit designed to research Microsoft Pre-Vista licensing mechanisms
A minimal GPU design in Verilog to learn how GPUs work from the ground up
A lightweight, durable, versatile runtime library for C++
SeaweedFS is a distributed storage system for object storage (S3), file systems, and Iceberg tables, designed to handle billions of files with O(1) disk access and effortless horizontal scaling.
2GHz single-ended active probe design
Reverse Engineering: Decompiling Binary Code with Large Language Models
Board design files of a PCIe interposer with SMA outputs
Guide to using the hardware PTP support in the Raspberry Pi CM4 and CM5
BaseJump STL: A Standard Template Library for SystemVerilog
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
Extract files from any kind of container formats
bitaxe based on the BM1366 ASIC from the Antminer S19 XP
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
Open source FPGA-based NIC and platform for in-network compute
Mechanical models and drawings of Xilinx VCU1525 board, heatsink and other hardware.
This repository contains Design files for Various Base board Designed for Avnet Zynq Ultrascale+ FPGA SOC
[MIRROR] unofficial implementation of Dante protocol (Audio over IP)
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps