OpenMMLab Model Deployment Framework

A primitive library for neural network

Boost.org asio module

JSON for Modern C++

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Vitis Libraries

PicoRV32 - A Size-Optimized RISC-V CPU

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Header-only C++ binding for libzmq

Wrapper for Rocket-Chip on FPGAs

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Open-source high-performance RISC-V processor

OpenHarmony documentation | OpenHarmony开发者文档

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Working draft of the proposed RISC-V V vector extension

Dataflow compiler for QNN inference on FPGAs

Vivado HLS library for FINN

paper implement

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

FPGA Accelerator for CNN using Vivado HLS

The Ultra-Low Power RISC-V Core

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

K210 PCB YOLO

Binarized Convolutional Neural Networks on Software-Programmable FPGAs