PhD graduated from USTC // FPGA // Verilog // Data Compression // LLM newbie // Hope to bring better open source projects. Welcome to report bugs.
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Univ. of Sci. & Tech. of China (USTC)
- China
- https://orcid.org/0000-0003-3065-4606
- https://gitee.com/wangxuan95
- https://www.zhihu.com/people/wang-xuan-12-89/posts
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written in VHDL
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A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
An open-source laser communication suite for 100Mbps Ethernet