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1. ucb-bar/chipyard ucb-bar/chipyard Public

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala 2.3k 890

2. eugene-tarassov/vivado-risc-v eugene-tarassov/vivado-risc-v Public

   Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

   Tcl 1.1k 249

3. SpinalHDL-Eval SpinalHDL-Eval Public

   An evaluation benchmark for the Spinalhdl code generation capability of LLM

   SystemVerilog 2

4. HDL-Agent HDL-Agent Public

   基于 CrewAI构建的面向 HDL 开发（SpinalHDL / Verilog / Chisel）的“检索增强生成 + 转换 + 验证 + 失败反馈重生成”闭环自动化Agent。

   Python

5. MinerU-PDFHub MinerU-PDFHub Public

   an on-premises MCP (Model Context Protocol) server for managing and serving documentation of private/internal libraries

   Nim

6. QuadPipe QuadPipe Public

   A Low-Error and High-Throughput Softmax Accelerator for Large Model Inference on FPGA

   SystemVerilog 1 1