metis-riscv

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1. ariane ariane Public

   Forked from openhwgroup/cva6

   Ariane is a 6-stage RISC-V CPU capable of booting Linux

   SystemVerilog

2. riscv-cores-list riscv-cores-list Public

   Forked from riscvarchive/riscv-cores-list

   RISC-V Cores, SoC platforms and SoCs

3. riscy-OOO riscy-OOO Public

   Forked from csail-csg/riscy-OOO

   RiscyOO: RISC-V Out-of-Order Processor

   Bluespec

4. RV12 RV12 Public

   Forked from RoaLogic/RV12

   RISC-V CPU Core

   SystemVerilog

5. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

   SystemVerilog

6. ridecore ridecore Public

   Forked from ridecore/ridecore

   RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

   Verilog