LUNA is a fast and efficient superconducting qubit readout accelerator that combines low-cost integrator-based preprocessing with Look-Up Table (LUT) based neural networks for classification. The architecture uses simple integrators for dimensionality reduction with minimal hardware overhead, and employs LogicNets (DNNs synthesized into LUT logic) to drastically reduce resource usage while enabling ultra-low-latency inference. We integrate this with a differential evolution based exploration and optimization framework to identify high-quality design points. Our results show up to a 10.95× reduction in area and 30% lower latency with little to no loss in fidelity compared to the state-of-the-art.
logicnets\experiments\binary_classification contains the code and instruction for setting up the differential evolution script and subsequent model training
preprocessor contains the adder tree templates
quantum-net-final contains final designs. Top level verilog file in each directory is readout_ip.sv. Vivado project files are also present, but designs were compiled using the run.tcl scripts